Lines Matching full:x

50 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
51 	FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
52 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
53 	FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
56 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
57 	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
58 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
59 	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
62 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
63 	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
64 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
65 	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
73 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
74 	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
75 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
76 	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
79 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
80 	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
81 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
82 	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
85 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
86 	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
87 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
88 	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
91 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
92 	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
93 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
94 	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
97 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
98 	FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
99 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
100 	FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
108 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
109 	FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
110 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
111 	FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
119 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
120 	FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
121 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
122 	FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
130 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
131 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
132 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
133 	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
136 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
137 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
138 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
139 	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
142 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
143 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
144 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
145 	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
148 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
149 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
150 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
151 	FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
154 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
155 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
156 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
157 	FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
160 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
161 	FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
162 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
163 	FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
171 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
172 	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
173 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
174 	FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
177 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
178 	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
179 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
180 	FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
183 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
184 	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
185 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
186 	FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
189 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
190 	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
191 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
192 	FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
195 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
196 	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
197 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
198 	FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
206 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
207 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
208 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
209 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
212 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
213 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
214 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
215 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
218 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
219 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
220 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
221 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
224 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
225 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
226 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
227 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
230 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
231 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
232 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
233 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
236 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
237 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
238 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
239 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
242 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
243 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
244 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
245 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
248 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
249 	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
250 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
251 	FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
259 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
260 	FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
261 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
262 	FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
265 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
266 	FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
267 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
268 	FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
276 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
277 	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
278 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
279 	FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
282 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
283 	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
284 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
285 	FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
288 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
289 	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
290 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
291 	FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
294 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
295 	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
296 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
297 	FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
305 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
306 	FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
307 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
308 	FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
316 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
317 	FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
318 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
319 	FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
322 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
323 	FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
324 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
325 	FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
328 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
329 	FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
330 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
331 	FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
339 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
340 	FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
341 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
342 	FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
350 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
351 	FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
352 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
353 	FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
361 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
362 	FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
363 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
364 	FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
372 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
373 	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
374 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
375 	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
378 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
379 	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
380 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
381 	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
384 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
385 	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
386 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
387 	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
390 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
391 	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
392 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
393 	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
396 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
397 	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
398 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
399 	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
407 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
408 	FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
409 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
410 	FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
418 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
419 	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
420 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
421 	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
424 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
425 	FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
426 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
427 	FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
430 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
431 	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
432 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
433 	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
436 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
437 	FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
438 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
439 	FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
442 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
443 	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
444 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
445 	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
453 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
454 	FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
455 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
456 	FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
459 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
460 	FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
461 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
462 	FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
470 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
471 	FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
472 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
473 	FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
481 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
482 	FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
483 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
484 	FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
487 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
488 	FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
489 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
490 	FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
498 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
499 	FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
500 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
501 	FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
504 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
505 	FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
506 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
507 	FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
515 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
516 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
517 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
518 	FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
521 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
522 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
523 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
524 	FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
527 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
528 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
529 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
530 	FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
533 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
534 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
535 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
536 	FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
539 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
540 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
541 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
542 	FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
545 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
546 	FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
547 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
548 	FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
556 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
557 	FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
558 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
559 	FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
562 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
563 	FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
564 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
565 	FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
573 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
574 	FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
575 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
576 	FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
579 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
580 	FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
581 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
582 	FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
590 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
591 	FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
592 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
593 	FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
596 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
597 	FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
598 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
599 	FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
607 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
608 	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
609 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
610 	FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
613 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
614 	FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
615 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
616 	FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
619 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
620 	FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
621 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
622 	FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
625 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
626 	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
627 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
628 	FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
631 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
632 	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
633 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
634 	FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
642 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
643 	FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
644 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
645 	FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
648 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
649 	FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
650 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
651 	FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
654 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
655 	FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
656 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
657 	FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
660 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
661 	FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
662 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
663 	FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
671 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
672 	FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
673 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
674 	FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
677 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
678 	FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
679 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
680 	FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
688 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
689 	FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
690 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
691 	FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
694 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
695 	FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
696 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
697 	FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
705 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
706 	FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
707 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
708 	FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
711 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
712 	FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
713 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
714 	FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
722 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
723 	FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
724 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
725 	FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
733 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
734 	FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
735 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
736 	FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
744 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
745 	FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
746 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
747 	FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
750 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
751 	FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
752 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
753 	FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
761 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
762 	FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
763 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
764 	FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
767 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
768 	FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
769 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
770 	FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
773 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
774 	FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
775 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
776 	FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
784 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
785 	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
786 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
787 	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
790 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
791 	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
792 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
793 	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
796 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
797 	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
798 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
799 	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
802 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
803 	FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
804 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
805 	FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
808 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
809 	FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
810 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
811 	FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
819 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
820 	FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
821 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
822 	FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
830 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
831 	FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
832 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
833 	FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
836 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
837 	FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
838 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
839 	FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
842 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
843 	FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
844 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
845 	FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
848 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
849 	FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
850 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
851 	FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
854 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
855 	FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
856 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
857 	FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
860 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
861 	FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
862 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
863 	FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
866 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
867 	FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
868 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
869 	FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
877 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
878 	FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
879 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
880 	FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
883 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
884 	FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
885 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
886 	FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
889 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
890 	FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
891 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
892 	FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
895 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
896 	FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
897 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
898 	FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
901 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
902 	FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
903 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
904 	FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
907 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
908 	FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
909 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
910 	FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
913 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
914 	FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
915 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
916 	FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
919 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
920 	FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
921 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
922 	FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
930 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
931 	FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
932 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
933 	FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
936 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
937 	FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
938 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
939 	FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
942 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
943 	FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
944 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
945 	FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
948 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
949 	FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
950 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
951 	FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
954 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
955 	FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
956 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
957 	FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
965 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
966 	FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
967 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
968 	FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
971 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
972 	FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
973 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
974 	FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
977 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
978 	FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
979 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
980 	FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
988 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
989 	FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
990 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
991 	FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
994 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
995 	FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
996 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
997 	FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
1000 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
1001 	FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1002 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
1003 	FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
1006 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
1007 	FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1008 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
1009 	FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
1012 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
1013 	FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1014 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
1015 	FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
1023 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
1024 	FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1025 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
1026 	FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
1034 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
1035 	FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
1036 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
1037 	FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
1040 #define SD10G_LANE_LANE_DF_LOL_SET(x)\
1041 	FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
1042 #define SD10G_LANE_LANE_DF_LOL_GET(x)\
1043 	FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
1046 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
1047 	FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1048 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
1049 	FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
1052 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
1053 	FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
1054 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
1055 	FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
1063 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
1064 	FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1065 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
1066 	FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
1069 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
1070 	FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1071 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
1072 	FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
1075 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
1076 	FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1077 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
1078 	FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
1081 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
1082 	FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1083 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
1084 	FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
1087 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
1088 	FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1089 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
1090 	FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
1098 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
1099 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1100 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
1101 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
1104 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\
1105 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1106 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\
1107 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
1110 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\
1111 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1112 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\
1113 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
1116 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\
1117 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1118 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\
1119 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
1122 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\
1123 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1124 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\
1125 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
1128 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\
1129 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1130 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\
1131 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
1134 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\
1135 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1136 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\
1137 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
1140 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\
1141 	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1142 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\
1143 	FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
1151 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\
1152 	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1153 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\
1154 	FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
1157 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\
1158 	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1159 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\
1160 	FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
1163 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\
1164 	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1165 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\
1166 	FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
1169 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\
1170 	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1171 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\
1172 	FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
1175 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\
1176 	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1177 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\
1178 	FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
1186 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\
1187 	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1188 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\
1189 	FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
1192 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\
1193 	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1194 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\
1195 	FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
1198 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\
1199 	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1200 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\
1201 	FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
1204 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\
1205 	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1206 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\
1207 	FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
1210 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\
1211 	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1212 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\
1213 	FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
1221 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\
1222 	FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1223 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\
1224 	FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
1227 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\
1228 	FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1229 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\
1230 	FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
1238 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\
1239 	FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1240 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\
1241 	FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
1244 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\
1245 	FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1246 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\
1247 	FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)
1255 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\
1256 	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1257 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\
1258 	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
1261 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\
1262 	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1263 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\
1264 	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
1267 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\
1268 	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1269 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\
1270 	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
1273 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\
1274 	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1275 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\
1276 	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
1284 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\
1285 	FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1286 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\
1287 	FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)
1290 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\
1291 	FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1292 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\
1293 	FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
1301 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\
1302 	FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1303 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\
1304 	FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
1307 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\
1308 	FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1309 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\
1310 	FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
1313 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\
1314 	FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1315 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\
1316 	FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
1319 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\
1320 	FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1321 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\
1322 	FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
1330 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\
1331 	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1332 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\
1333 	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
1336 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\
1337 	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1338 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\
1339 	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
1342 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\
1343 	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1344 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\
1345 	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
1353 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1354 	FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1355 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1356 	FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
1359 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\
1360 	FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1361 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\
1362 	FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
1370 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\
1371 	FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1372 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\
1373 	FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
1381 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\
1382 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1383 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\
1384 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
1387 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\
1388 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1389 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\
1390 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
1393 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\
1394 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1395 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\
1396 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
1399 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\
1400 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1401 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\
1402 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
1405 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\
1406 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1407 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\
1408 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
1411 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\
1412 	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1413 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\
1414 	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
1422 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\
1423 	FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1424 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\
1425 	FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
1433 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\
1434 	FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1435 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\
1436 	FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
1444 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\
1445 	FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1446 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\
1447 	FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
1450 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\
1451 	FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1452 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\
1453 	FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
1461 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\
1462 	FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1463 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\
1464 	FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
1472 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\
1473 	FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1474 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\
1475 	FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
1478 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\
1479 	FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1480 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\
1481 	FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
1489 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
1490 	FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1491 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
1492 	FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
1495 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\
1496 	FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1497 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\
1498 	FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
1506 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\
1507 	FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1508 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\
1509 	FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
1517 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\
1518 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1519 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\
1520 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
1523 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\
1524 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1525 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\
1526 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
1529 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\
1530 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1531 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\
1532 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
1535 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\
1536 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1537 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\
1538 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
1541 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\
1542 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1543 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\
1544 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
1547 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\
1548 	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1549 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\
1550 	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
1558 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\
1559 	FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1560 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\
1561 	FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
1564 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\
1565 	FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1566 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\
1567 	FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
1575 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\
1576 	FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1577 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\
1578 	FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
1581 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\
1582 	FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1583 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\
1584 	FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
1592 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\
1593 	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1594 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\
1595 	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
1598 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\
1599 	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1600 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\
1601 	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
1604 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\
1605 	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1606 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\
1607 	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
1615 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\
1616 	FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1617 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\
1618 	FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
1626 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\
1627 	FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1628 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\
1629 	FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
1637 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\
1638 	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1639 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\
1640 	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
1643 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\
1644 	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1645 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\
1646 	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
1649 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\
1650 	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1651 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\
1652 	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
1660 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
1661 	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1662 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
1663 	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
1666 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\
1667 	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1668 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\
1669 	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
1672 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\
1673 	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1674 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\
1675 	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
1683 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\
1684 	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1685 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\
1686 	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
1689 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\
1690 	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1691 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\
1692 	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
1695 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\
1696 	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1697 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\
1698 	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
1701 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\
1702 	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1703 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\
1704 	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
1707 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\
1708 	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1709 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\
1710 	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
1718 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\
1719 	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1720 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\
1721 	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
1724 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\
1725 	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1726 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\
1727 	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
1730 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\
1731 	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1732 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\
1733 	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
1736 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\
1737 	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1738 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\
1739 	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
1747 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\
1748 	FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1749 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\
1750 	FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
1758 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\
1759 	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1760 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\
1761 	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
1764 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\
1765 	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1766 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\
1767 	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
1770 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\
1771 	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1772 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\
1773 	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
1776 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\
1777 	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1778 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\
1779 	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
1782 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\
1783 	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1784 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\
1785 	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
1793 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\
1794 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1795 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\
1796 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
1799 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\
1800 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1801 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\
1802 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
1805 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\
1806 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1807 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\
1808 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
1811 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\
1812 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1813 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\
1814 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
1817 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\
1818 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1819 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\
1820 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
1823 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\
1824 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1825 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\
1826 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
1829 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\
1830 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1831 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\
1832 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
1835 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\
1836 	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1837 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\
1838 	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
1846 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\
1847 	FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1848 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\
1849 	FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
1852 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\
1853 	FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1854 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\
1855 	FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
1863 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\
1864 	FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1865 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\
1866 	FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
1874 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\
1875 	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1876 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\
1877 	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
1880 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\
1881 	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1882 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\
1883 	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
1886 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\
1887 	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1888 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\
1889 	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
1892 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\
1893 	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1894 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\
1895 	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
1903 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\
1904 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1905 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\
1906 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
1909 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\
1910 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1911 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\
1912 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
1915 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\
1916 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1917 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\
1918 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
1921 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\
1922 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1923 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\
1924 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
1927 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\
1928 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1929 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\
1930 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
1933 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\
1934 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1935 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\
1936 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
1939 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\
1940 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1941 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\
1942 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
1945 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\
1946 	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1947 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\
1948 	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
1956 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\
1957 	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1958 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\
1959 	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
1962 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\
1963 	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1964 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\
1965 	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
1968 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\
1969 	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1970 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\
1971 	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
1974 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\
1975 	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1976 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\
1977 	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
1980 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\
1981 	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1982 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\
1983 	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
1991 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\
1992 	FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
1993 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\
1994 	FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
2002 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\
2003 	FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2004 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\
2005 	FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
2013 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\
2014 	FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2015 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\
2016 	FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
2024 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\
2025 	FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2026 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\
2027 	FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
2035 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\
2036 	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2037 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\
2038 	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
2041 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\
2042 	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2043 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\
2044 	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
2047 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\
2048 	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2049 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\
2050 	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
2053 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\
2054 	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2055 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\
2056 	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
2064 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\
2065 	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2066 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\
2067 	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
2070 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\
2071 	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2072 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\
2073 	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
2076 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\
2077 	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2078 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\
2079 	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
2087 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\
2088 	FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2089 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\
2090 	FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
2093 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\
2094 	FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2095 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\
2096 	FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
2104 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\
2105 	FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2106 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\
2107 	FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
2110 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\
2111 	FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2112 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\
2113 	FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
2121 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\
2122 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2123 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\
2124 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
2127 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\
2128 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2129 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\
2130 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
2133 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\
2134 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2135 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\
2136 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
2139 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\
2140 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2141 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\
2142 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
2145 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\
2146 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2147 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\
2148 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
2151 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\
2152 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2153 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\
2154 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
2157 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\
2158 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2159 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\
2160 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
2163 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\
2164 	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2165 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\
2166 	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
2174 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\
2175 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2176 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\
2177 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
2180 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\
2181 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2182 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\
2183 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
2186 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\
2187 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2188 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\
2189 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
2192 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\
2193 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2194 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\
2195 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
2198 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\
2199 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2200 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\
2201 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
2204 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\
2205 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2206 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\
2207 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
2210 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\
2211 	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2212 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\
2213 	FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
2221 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\
2222 	FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2223 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\
2224 	FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
2232 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\
2233 	FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2234 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\
2235 	FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
2243 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\
2244 	FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2245 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\
2246 	FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
2254 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\
2255 	FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2256 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\
2257 	FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
2265 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\
2266 	FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2267 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\
2268 	FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
2271 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\
2272 	FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
2273 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\
2274 	FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)
2277 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\
2278 	FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2279 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\
2280 	FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
2283 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\
2284 	FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2285 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\
2286 	FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
2294 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\
2295 	FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
2296 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\
2297 	FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)
2300 #define SD6G_LANE_LANE_DF_LOL_SET(x)\
2301 	FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2302 #define SD6G_LANE_LANE_DF_LOL_GET(x)\
2303 	FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
2306 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
2307 	FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2308 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
2309 	FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
2312 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\
2313 	FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
2314 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\
2315 	FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)
2322 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\
2323 	FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2324 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\
2325 	FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
2328 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\
2329 	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2330 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\
2331 	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
2334 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\
2335 	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2336 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\
2337 	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
2340 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\
2341 	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2342 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\
2343 	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
2350 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\
2351 	FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2352 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\
2353 	FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
2356 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\
2357 	FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2358 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\
2359 	FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
2366 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\
2367 	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)
2368 #define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\
2369 	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)
2372 #define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\
2373 	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)
2374 #define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\
2375 	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)
2378 #define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\
2379 	FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
2380 #define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\
2381 	FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)
2384 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\
2385 	FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2386 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\
2387 	FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
2390 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\
2391 	FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2392 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\
2393 	FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
2396 #define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\
2397 	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)
2398 #define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\
2399 	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)
2402 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\
2403 	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2404 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\
2405 	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
2408 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\
2409 	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2410 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\
2411 	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
2418 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\
2419 	FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2420 #define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\
2421 	FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
2424 #define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\
2425 	FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2426 #define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\
2427 	FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
2430 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\
2431 	FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2432 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\
2433 	FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
2436 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\
2437 	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2438 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\
2439 	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
2442 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\
2443 	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2444 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\
2445 	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
2452 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\
2453 	FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2454 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\
2455 	FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
2458 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\
2459 	FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2460 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\
2461 	FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
2464 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\
2465 	FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2466 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\
2467 	FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)
2470 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\
2471 	FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
2472 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\
2473 	FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)
2480 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\
2481 	FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2482 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\
2483 	FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
2486 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\
2487 	FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2488 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\
2489 	FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
2492 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\
2493 	FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2494 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\
2495 	FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
2498 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\
2499 	FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2500 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\
2501 	FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)
2504 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\
2505 	FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2506 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\
2507 	FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
2514 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\
2515 	FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2516 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\
2517 	FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
2524 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\
2525 	FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2526 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\
2527 	FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
2530 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\
2531 	FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2532 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\
2533 	FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
2536 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\
2537 	FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2538 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\
2539 	FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
2542 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\
2543 	FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2544 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\
2545 	FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
2552 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\
2553 	FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2554 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\
2555 	FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
2562 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\
2563 	FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
2564 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\
2565 	FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)
2568 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\
2569 	FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
2570 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\
2571 	FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)
2578 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\
2579 	FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2580 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\
2581 	FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
2584 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\
2585 	FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2586 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\
2587 	FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
2590 #define SD_CMU_CMU_45_RESERVED_SET(x)\
2591 	FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2592 #define SD_CMU_CMU_45_RESERVED_GET(x)\
2593 	FIELD_GET(SD_CMU_CMU_45_RESERVED, x)
2596 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\
2597 	FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2598 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\
2599 	FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
2602 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\
2603 	FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
2604 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\
2605 	FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)
2608 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\
2609 	FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2610 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\
2611 	FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
2614 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\
2615 	FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2616 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\
2617 	FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
2620 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\
2621 	FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2622 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\
2623 	FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
2630 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\
2631 	FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2632 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\
2633 	FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
2640 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\
2641 	FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2642 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\
2643 	FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
2646 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\
2647 	FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2648 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\
2649 	FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
2657 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\
2658 	FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2659 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\
2660 	FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
2663 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\
2664 	FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2665 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\
2666 	FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
2673 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\
2674 	FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
2675 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\
2676 	FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)
2683 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\
2684 	FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
2685 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\
2686 	FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)
2693 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\
2694 	FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2695 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\
2696 	FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
2699 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2700 	FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2701 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2702 	FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
2705 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\
2706 	FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2707 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\
2708 	FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
2711 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\
2712 	FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2713 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\
2714 	FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
2717 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\
2718 	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2719 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\
2720 	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)
2723 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\
2724 	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2725 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\
2726 	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
2729 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\
2730 	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2731 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\
2732 	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
2739 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
2740 	FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2741 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
2742 	FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
2745 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\
2746 	FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2747 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\
2748 	FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
2751 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\
2752 	FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2753 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\
2754 	FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
2761 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\
2762 	FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2763 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\
2764 	FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
2771 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\
2772 	FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
2773 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\
2774 	FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)
2777 #define SD_LANE_MISC_RX_ENA_SET(x)\
2778 	FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
2779 #define SD_LANE_MISC_RX_ENA_GET(x)\
2780 	FIELD_GET(SD_LANE_MISC_RX_ENA, x)
2783 #define SD_LANE_MISC_MUX_ENA_SET(x)\
2784 	FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
2785 #define SD_LANE_MISC_MUX_ENA_GET(x)\
2786 	FIELD_GET(SD_LANE_MISC_MUX_ENA, x)
2790 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\
2791 	FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
2792 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\
2793 	FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)
2800 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\
2801 	FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2802 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\
2803 	FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
2806 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\
2807 	FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2808 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\
2809 	FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
2817 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\
2818 	FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2819 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\
2820 	FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)
2828 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\
2829 	FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2830 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\
2831 	FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)
2839 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\
2840 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2841 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\
2842 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
2845 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
2846 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2847 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
2848 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
2851 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\
2852 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2853 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\
2854 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
2857 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\
2858 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2859 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\
2860 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
2863 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\
2864 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2865 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\
2866 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
2869 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\
2870 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2871 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\
2872 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
2875 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\
2876 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2877 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\
2878 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
2881 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\
2882 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2883 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\
2884 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
2887 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\
2888 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2889 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\
2890 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
2893 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\
2894 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2895 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\
2896 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
2899 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\
2900 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2901 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\
2902 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
2905 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\
2906 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2907 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\
2908 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
2911 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\
2912 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2913 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\
2914 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
2917 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\
2918 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2919 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\
2920 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
2923 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\
2924 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2925 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\
2926 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
2929 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\
2930 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2931 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\
2932 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
2940 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\
2941 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2942 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\
2943 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
2946 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\
2947 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2948 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\
2949 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
2952 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\
2953 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2954 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\
2955 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
2958 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\
2959 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2960 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\
2961 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
2964 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\
2965 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2966 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\
2967 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
2970 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\
2971 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2972 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\
2973 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
2976 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\
2977 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2978 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\
2979 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
2982 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\
2983 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2984 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\
2985 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
2988 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\
2989 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2990 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\
2991 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
2994 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\
2995 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
2996 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\
2997 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
3000 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\
3001 	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3002 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\
3003 	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
3011 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
3012 	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3013 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
3014 	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
3017 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\
3018 	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3019 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\
3020 	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
3023 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\
3024 	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3025 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\
3026 	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
3034 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\
3035 	FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
3036 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\
3037 	FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)