Lines Matching full:x

21 #define HSIO_SD_CFG_PHY_RESET_SET(x)\
22 	FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
23 #define HSIO_SD_CFG_PHY_RESET_GET(x)\
24 	FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
27 #define HSIO_SD_CFG_TX_RESET_SET(x)\
28 	FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
29 #define HSIO_SD_CFG_TX_RESET_GET(x)\
30 	FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
33 #define HSIO_SD_CFG_TX_RATE_SET(x)\
34 	FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
35 #define HSIO_SD_CFG_TX_RATE_GET(x)\
36 	FIELD_GET(HSIO_SD_CFG_TX_RATE, x)
39 #define HSIO_SD_CFG_TX_INVERT_SET(x)\
40 	FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
41 #define HSIO_SD_CFG_TX_INVERT_GET(x)\
42 	FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)
45 #define HSIO_SD_CFG_TX_EN_SET(x)\
46 	FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
47 #define HSIO_SD_CFG_TX_EN_GET(x)\
48 	FIELD_GET(HSIO_SD_CFG_TX_EN, x)
51 #define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
52 	FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
53 #define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
54 	FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)
57 #define HSIO_SD_CFG_TX_CM_EN_SET(x)\
58 	FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
59 #define HSIO_SD_CFG_TX_CM_EN_GET(x)\
60 	FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)
63 #define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
64 	FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
65 #define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
66 	FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)
69 #define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
70 	FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
71 #define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
72 	FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)
75 #define HSIO_SD_CFG_RX_RESET_SET(x)\
76 	FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
77 #define HSIO_SD_CFG_RX_RESET_GET(x)\
78 	FIELD_GET(HSIO_SD_CFG_RX_RESET, x)
81 #define HSIO_SD_CFG_RX_RATE_SET(x)\
82 	FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
83 #define HSIO_SD_CFG_RX_RATE_GET(x)\
84 	FIELD_GET(HSIO_SD_CFG_RX_RATE, x)
87 #define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
88 	FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
89 #define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
90 	FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)
93 #define HSIO_SD_CFG_RX_INVERT_SET(x)\
94 	FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
95 #define HSIO_SD_CFG_RX_INVERT_GET(x)\
96 	FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)
99 #define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
100 	FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
101 #define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
102 	FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)
105 #define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
106 	FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
107 #define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
108 	FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
114 #define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
115 	FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
116 #define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
117 	FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)
120 #define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
121 	FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
122 #define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
123 	FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)
126 #define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
127 	FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
128 #define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
129 	FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)
132 #define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
133 	FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
134 #define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
135 	FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
141 #define HSIO_SD_STAT_MPLL_STATE_SET(x)\
142 	FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
143 #define HSIO_SD_STAT_MPLL_STATE_GET(x)\
144 	FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)
147 #define HSIO_SD_STAT_TX_STATE_SET(x)\
148 	FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
149 #define HSIO_SD_STAT_TX_STATE_GET(x)\
150 	FIELD_GET(HSIO_SD_STAT_TX_STATE, x)
153 #define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
154 	FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
155 #define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
156 	FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)
159 #define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
160 	FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
161 #define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
162 	FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)
168 #define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
169 	(((x) << 15) & GENMASK(15, 15))
170 #define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
171 	FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)
174 #define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
175 	(((x) << 14) & GENMASK(14, 14))
176 #define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
177 	FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)
180 #define HSIO_HW_CFG_RGMII_ENA_SET(x)\
181 	(((x) << 12) & GENMASK(13, 12))
182 #define HSIO_HW_CFG_RGMII_ENA_GET(x)\
183 	FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)
186 #define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
187 	(((x) << 11) & GENMASK(11, 11))
188 #define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
189 	FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)
192 #define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
193 	(((x) << 10) & GENMASK(10, 10))
194 #define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
195 	FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)
198 #define HSIO_HW_CFG_GMII_ENA_SET(x)\
199 	(((x) << 2) & GENMASK(9, 2))
200 #define HSIO_HW_CFG_GMII_ENA_GET(x)\
201 	FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)
204 #define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
205 	((x) & GENMASK(1, 0))
206 #define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
207 	FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
213 #define HSIO_RGMII_CFG_TX_CLK_CFG_SET(x)\
214 	FIELD_PREP(HSIO_RGMII_CFG_TX_CLK_CFG, x)
215 #define HSIO_RGMII_CFG_TX_CLK_CFG_GET(x)\
216 	FIELD_GET(HSIO_RGMII_CFG_TX_CLK_CFG, x)
219 #define HSIO_RGMII_CFG_RGMII_TX_RST_SET(x)\
220 	FIELD_PREP(HSIO_RGMII_CFG_RGMII_TX_RST, x)
221 #define HSIO_RGMII_CFG_RGMII_TX_RST_GET(x)\
222 	FIELD_GET(HSIO_RGMII_CFG_RGMII_TX_RST, x)
225 #define HSIO_RGMII_CFG_RGMII_RX_RST_SET(x)\
226 	FIELD_PREP(HSIO_RGMII_CFG_RGMII_RX_RST, x)
227 #define HSIO_RGMII_CFG_RGMII_RX_RST_GET(x)\
228 	FIELD_GET(HSIO_RGMII_CFG_RGMII_RX_RST, x)
234 #define HSIO_DLL_CFG_DELAY_ENA_SET(x)\
235 	FIELD_PREP(HSIO_DLL_CFG_DELAY_ENA, x)
236 #define HSIO_DLL_CFG_DELAY_ENA_GET(x)\
237 	FIELD_GET(HSIO_DLL_CFG_DELAY_ENA, x)
240 #define HSIO_DLL_CFG_DLL_ENA_SET(x)\
241 	FIELD_PREP(HSIO_DLL_CFG_DLL_ENA, x)
242 #define HSIO_DLL_CFG_DLL_ENA_GET(x)\
243 	FIELD_GET(HSIO_DLL_CFG_DLL_ENA, x)
246 #define HSIO_DLL_CFG_DLL_RST_SET(x)\
247 	FIELD_PREP(HSIO_DLL_CFG_DLL_RST, x)
248 #define HSIO_DLL_CFG_DLL_RST_GET(x)\
249 	FIELD_GET(HSIO_DLL_CFG_DLL_RST, x)