phy/mediatek/phy-mtk-tphy.c

682 	struct mtk_phy_instance *instance)
684 	struct u2phy_banks *u2_banks = &instance->u2_banks;
698 	if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef)
713 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
742 		instance->index, fm_out, calibration_val,
754 	struct mtk_phy_instance *instance)
756 	struct u3phy_banks *u3_banks = &instance->u3_banks;
760 	if (instance->type_force_mode) {
799 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
803 	struct mtk_phy_instance *instance)
805 	struct u2phy_banks *u2_banks = &instance->u2_banks;
822 	struct mtk_phy_instance *instance)
824 	struct u2phy_banks *u2_banks = &instance->u2_banks;
826 	u32 index = instance->index;
862 	u2_phy_pll_26m_set(tphy, instance);
868 	struct mtk_phy_instance *instance)
870 	struct u2phy_banks *u2_banks = &instance->u2_banks;
872 	u32 index = instance->index;
890 	struct mtk_phy_instance *instance)
892 	struct u2phy_banks *u2_banks = &instance->u2_banks;
894 	u32 index = instance->index;
913 	struct mtk_phy_instance *instance)
915 	struct u2phy_banks *u2_banks = &instance->u2_banks;
917 	u32 index = instance->index;
927 				     struct mtk_phy_instance *instance,
930 	struct u2phy_banks *u2_banks = &instance->u2_banks;
952 	struct mtk_phy_instance *instance)
954 	struct u3phy_banks *u3_banks = &instance->u3_banks;
998 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1002 	struct mtk_phy_instance *instance)
1004 	struct u3phy_banks *bank = &instance->u3_banks;
1014 	struct mtk_phy_instance *instance)
1017 	struct u3phy_banks *bank = &instance->u3_banks;
1027 	struct mtk_phy_instance *instance)
1029 	struct u3phy_banks *u3_banks = &instance->u3_banks;
1068 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1072 			      struct mtk_phy_instance *instance)
1074 	struct u2phy_banks *u2_banks = &instance->u2_banks;
1075 	struct u3phy_banks *u3_banks = &instance->u3_banks;
1077 	switch (instance->type) {
1081 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
1087 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1088 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
1091 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1100 			      struct mtk_phy_instance *instance)
1102 	struct u2phy_banks *u2_banks = &instance->u2_banks;
1103 	struct u3phy_banks *u3_banks = &instance->u3_banks;
1105 	switch (instance->type) {
1107 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
1108 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
1109 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
1113 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
1114 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
1115 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
1116 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
1125 				struct mtk_phy_instance *instance)
1127 	struct device *dev = &instance->phy->dev;
1129 	if (instance->type == PHY_TYPE_USB3)
1130 		instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");
1132 	if (instance->type != PHY_TYPE_USB2)
1135 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
1137 				 &instance->eye_src);
1139 				 &instance->eye_vrt);
1141 				 &instance->eye_term);
1143 				 &instance->intr);
1145 				 &instance->discth);
1147 				 &instance->pre_emphasis);
1149 		instance->bc12_en, instance->eye_src,
1150 		instance->eye_vrt, instance->eye_term,
1151 		instance->intr, instance->discth);
1152 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
1156 			     struct mtk_phy_instance *instance)
1158 	struct u2phy_banks *u2_banks = &instance->u2_banks;
1161 	if (instance->bc12_en) /* BC1.2 path Enable */
1164 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
1166 				     instance->eye_src);
1168 	if (instance->eye_vrt)
1170 				     instance->eye_vrt);
1172 	if (instance->eye_term)
1174 				     instance->eye_term);
1176 	if (instance->intr) {
1182 				     instance->intr);
1185 	if (instance->discth)
1187 				     instance->discth);
1189 	if (instance->pre_emphasis)
1191 				     instance->pre_emphasis);
1195 static int phy_type_syscon_get(struct mtk_phy_instance *instance,
1210 	instance->type_sw_reg = args.args[0];
1211 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
1212 	instance->type_sw = syscon_node_to_regmap(args.np);
1214 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
1215 		 instance->type_sw_reg, instance->type_sw_index);
1217 	return PTR_ERR_OR_ZERO(instance->type_sw);
1220 static int phy_type_set(struct mtk_phy_instance *instance)
1225 	if (!instance->type_sw)
1228 	switch (instance->type) {
1246 	offset = instance->type_sw_index * BITS_PER_BYTE;
1247 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
1253 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
1255 	struct device *dev = &instance->phy->dev;
1260 		instance->efuse_sw_en = 0;
1265 	instance->efuse_sw_en = device_property_present(dev, "nvmem-cells");
1266 	if (!instance->efuse_sw_en)
1269 	switch (instance->type) {
1271 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1278 		if (!instance->efuse_intr) {
1280 			instance->efuse_sw_en = 0;
1284 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
1289 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1295 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
1301 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
1308 		if (!instance->efuse_intr &&
1309 		    !instance->efuse_rx_imp &&
1310 		    !instance->efuse_tx_imp) {
1312 			instance->efuse_sw_en = 0;
1317 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
1320 		dev_err(dev, "no sw efuse for type %d\n", instance->type);
1327 static void phy_efuse_set(struct mtk_phy_instance *instance)
1329 	struct device *dev = &instance->phy->dev;
1330 	struct u2phy_banks *u2_banks = &instance->u2_banks;
1331 	struct u3phy_banks *u3_banks = &instance->u3_banks;
1333 	if (!instance->efuse_sw_en)
1336 	switch (instance->type) {
1341 				     instance->efuse_intr);
1348 				    instance->efuse_tx_imp);
1352 				    instance->efuse_rx_imp);
1356 				    instance->efuse_intr);
1359 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
1366 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1370 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1374 	phy_efuse_set(instance);
1376 	switch (instance->type) {
1378 		u2_phy_instance_init(tphy, instance);
1379 		u2_phy_props_set(tphy, instance);
1382 		u3_phy_instance_init(tphy, instance);
1385 		pcie_phy_instance_init(tphy, instance);
1388 		sata_phy_instance_init(tphy, instance);
1395 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1404 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1407 	if (instance->type == PHY_TYPE_USB2) {
1408 		u2_phy_instance_power_on(tphy, instance);
1409 		hs_slew_rate_calibrate(tphy, instance);
1410 	} else if (instance->type == PHY_TYPE_PCIE) {
1411 		pcie_phy_instance_power_on(tphy, instance);
1419 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1422 	if (instance->type == PHY_TYPE_USB2)
1423 		u2_phy_instance_power_off(tphy, instance);
1424 	else if (instance->type == PHY_TYPE_PCIE)
1425 		pcie_phy_instance_power_off(tphy, instance);
1432 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1435 	if (instance->type == PHY_TYPE_USB2)
1436 		u2_phy_instance_exit(tphy, instance);
1438 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1444 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1447 	if (instance->type == PHY_TYPE_USB2)
1448 		u2_phy_instance_set_mode(tphy, instance, mode);
1457 	struct mtk_phy_instance *instance = NULL;
1469 			instance = tphy->phys[index];
1473 	if (!instance) {
1478 	instance->type = args->args[0];
1479 	if (!(instance->type == PHY_TYPE_USB2 ||
1480 	      instance->type == PHY_TYPE_USB3 ||
1481 	      instance->type == PHY_TYPE_PCIE ||
1482 	      instance->type == PHY_TYPE_SATA ||
1483 	      instance->type == PHY_TYPE_SGMII)) {
1484 		dev_err(dev, "unsupported device type: %d\n", instance->type);
1490 		phy_v1_banks_init(tphy, instance);
1494 		phy_v2_banks_init(tphy, instance);
1501 	ret = phy_efuse_get(tphy, instance);
1505 	phy_parse_property(tphy, instance);
1506 	phy_type_set(instance);
1507 	phy_debugfs_init(instance);
1509 	return instance->phy;
1615 		struct mtk_phy_instance *instance;
1621 		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1622 		if (!instance)
1625 		tphy->phys[port] = instance;
1641 		instance->port_base = devm_ioremap_resource(subdev, &res);
1642 		if (IS_ERR(instance->port_base))
1643 			return PTR_ERR(instance->port_base);
1645 		instance->phy = phy;
1646 		instance->index = port;
1647 		phy_set_drvdata(phy, instance);
1650 		clks = instance->clks;
1657 		retval = phy_type_syscon_get(instance, child_np);