Lines Matching +full:50 +full:mhz

59 	unsigned int mhz;
84 	mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);
85 	if (mhz <= 200 && mhz >= 170)
87 	else if (mhz <= 170 && mhz >= 140)
89 	else if (mhz <= 140 && mhz >= 110)
91 	else if (mhz <= 110 && mhz >= 80)
93 	else if (mhz <= 80 && mhz >= 50)
99 	if (mhz > 175)
100 		dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
125 				       0, 50);
156 	if (mhz == 0)
161 	 * our source clock is at 50 MHz and that lock time scales linearly
171 	 * generous and give it 50ms.
175 				       0, 50 * USEC_PER_MSEC);