drivers/perf/qcom_l3_pmu.c

195 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
201 	gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
203 	writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);
207 	writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
208 	writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
214 	writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));
215 	writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
218 	writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));
219 	writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);
220 	writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
221 	writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
227 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
229 	u32 gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
232 	writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
233 	writel_relaxed(PMCNTENCLR(idx + 1), l3pmu->regs + L3_M_BC_CNTENCLR);
236 	writel_relaxed(gang & ~GANG_EN(idx + 1), l3pmu->regs + L3_M_BC_GANG);
241 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
249 			hi = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
250 			lo = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
251 		} while (hi != readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)));
276 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
279 	u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
282 	writel_relaxed(irqctl | PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
286 	writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
289 	writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
292 	writel_relaxed(PMINTENSET(idx), l3pmu->regs + L3_M_BC_INTENSET);
295 	writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
296 	writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
302 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
304 	u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
307 	writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
310 	writel_relaxed(PMINTENCLR(idx), l3pmu->regs + L3_M_BC_INTENCLR);
313 	writel_relaxed(irqctl & ~PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
318 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
324 		new = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
350 static inline void qcom_l3_cache__init(struct l3cache_pmu *l3pmu)
354 	writel_relaxed(BC_RESET, l3pmu->regs + L3_M_BC_CR);
360 	writel(BC_SATROLL_CR_RESET, l3pmu->regs + L3_M_BC_SATROLL_CR);
362 	writel_relaxed(BC_CNTENCLR_RESET, l3pmu->regs + L3_M_BC_CNTENCLR);
363 	writel_relaxed(BC_INTENCLR_RESET, l3pmu->regs + L3_M_BC_INTENCLR);
364 	writel_relaxed(PMOVSRCLR_RESET, l3pmu->regs + L3_M_BC_OVSR);
365 	writel_relaxed(BC_GANG_RESET, l3pmu->regs + L3_M_BC_GANG);
366 	writel_relaxed(BC_IRQCTL_RESET, l3pmu->regs + L3_M_BC_IRQCTL);
367 	writel_relaxed(PM_CR_RESET, l3pmu->regs + L3_HML3_PM_CR);
370 		writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(i));
371 		writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(i));
374 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRA);
375 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRAM);
376 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRB);
377 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRBM);
378 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRC);
379 	writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRCM);
385 	writel(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
390 	struct l3cache_pmu *l3pmu = data;
392 	long status = readl_relaxed(l3pmu->regs + L3_M_BC_OVSR);
399 	writel_relaxed(status, l3pmu->regs + L3_M_BC_OVSR);
405 		event = l3pmu->events[idx];
429 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
434 	writel_relaxed(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
439 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
441 	writel_relaxed(0, l3pmu->regs + L3_M_BC_CR);
480 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
519 	event->cpu = cpumask_first(&l3pmu->cpumask);
549 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
557 	idx = bitmap_find_free_region(l3pmu->used_mask, L3_NUM_COUNTERS, order);
564 	l3pmu->events[idx] = event;
577 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
583 	l3pmu->events[hwc->idx] = NULL;
584 	bitmap_release_region(l3pmu->used_mask, hwc->idx, order);
664 	struct l3cache_pmu *l3pmu = to_l3cache_pmu(dev_get_drvdata(dev));
666 	return cpumap_print_to_pagebuf(true, buf, &l3pmu->cpumask);
696 	struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
699 	if (cpumask_empty(&l3pmu->cpumask))
700 		cpumask_set_cpu(cpu, &l3pmu->cpumask);
707 	struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
710 	if (!cpumask_test_and_clear_cpu(cpu, &l3pmu->cpumask))
715 	perf_pmu_migrate_context(&l3pmu->pmu, cpu, target);
716 	cpumask_set_cpu(target, &l3pmu->cpumask);
722 	struct l3cache_pmu *l3pmu;
734 	l3pmu = devm_kzalloc(&pdev->dev, sizeof(*l3pmu), GFP_KERNEL);
738 	if (!l3pmu || !name)
741 	l3pmu->pmu = (struct pmu) {
758 	l3pmu->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &memrc);
759 	if (IS_ERR(l3pmu->regs))
760 		return PTR_ERR(l3pmu->regs);
762 	qcom_l3_cache__init(l3pmu);
769 			       name, l3pmu);
777 	ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, &l3pmu->node);
783 	ret = perf_pmu_register(&l3pmu->pmu, name, -1);
789 	dev_info(&pdev->dev, "Registered %s, type: %d\n", name, l3pmu->pmu.type);