Lines Matching +full:broken +full:- +full:udma
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags))
102 int ret = -ENOTTY;
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
173 if ((f->class == (u32) (dev->class >> f->class_shift) ||
174 f->class == (u32) PCI_ANY_ID) &&
175 (f->vendor == dev->vendor ||
176 f->vendor == (u16) PCI_ANY_ID) &&
177 (f->device == dev->device ||
178 f->device == (u16) PCI_ANY_ID)) {
181 hook = offset_to_ptr(&f->hook_offset);
183 hook = f->hook;
309 * key system devices. For devices that need to have mmio decoding always-on,
310 * we need to set the dev->mmio_always_on bit.
314 dev->mmio_always_on = 1;
327 * Deal with broken BIOSes that neglect to enable passive release,
355 * contacts at VIA ask them for me please -- Alan
402 /* Chipsets where PCI->PCI transfers vanish or hang */
440 * Made according to a Windows driver-based patch by George E. Breese;
442 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
461 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
465 if (p->revision < 0x40 || p->revision > 0x42)
473 if (p->revision < 0x10 || p->revision > 0x12)
486 * corruption without SB Live! but with things like 3 UDMA IDE
565 dev->cfg_size = 0xA0;
575 dev->cfg_size = 0x600;
588 struct resource *r = &dev->resource[i];
591 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
593 r->flags |= IORESOURCE_UNSET;
603 * If it's needed, re-allocate the region.
607 struct resource *r = &dev->resource[0];
609 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) {
610 r->flags |= IORESOURCE_UNSET;
630 res->name = pci_name(dev);
631 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
632 res->flags |=
634 region &= ~(size - 1);
638 bus_region.end = region + size - 1;
639 pcibios_bus_to_resource(dev->bus, res, &bus_region);
650 * CS553x's ISA PCI BARs may also be read-only (ref:
651 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
675 region &= ~(size - 1);
680 res->name = pci_name(dev);
681 res->flags = IORESOURCE_IO;
685 bus_region.end = region + size - 1;
686 pcibios_bus_to_resource(dev->bus, res, &bus_region);
691 * non-standard resource. Printing "nr" or pci_resource_name() of
700 * between 0x3b0->0x3bb or read 0x3d3
724 u32 class = pdev->class;
728 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
730 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
731 class, pdev->class);
742 * devices should use dwc3-haps driver. Change these devices' class code to
743 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
748 u32 class = pdev->class;
750 switch (pdev->device) {
754 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
755 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
756 class, pdev->class);
803 base &= -size;
804 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
829 base &= -size;
830 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
882 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
894 * here is really at that address. This happens on boards with broken
956 base &= ~(size-1);
962 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
970 /* ICH6-specific generic IO decode */
989 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
1001 /* ICH7-10 has the same common LPC generic IO decode registers */
1033 if (dev->revision & 0x10)
1050 "vt82c686 HW-mon");
1069 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1070 * back-to-back: Disable fast back-to-back on the secondary bus segment
1077 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
1078 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
1092 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1095 * TODO: When we have device-specific interrupt routers, this code will go
1105 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
1117 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1129 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1137 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1147 if (dev->revision >= 0x02) {
1159 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1160 if (dev->subsystem_device == 0xa118)
1161 dev->sriov->link = dev->devfn;
1168 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1172 if (dev->subordinate && dev->revision <= 0x12) {
1173 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1174 dev->revision);
1175 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1185 * -jgarzik
1195 d->irq = irq;
1201 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1206 switch (dev->device) {
1213 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1214 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1241 * quirk_via_vlink - VIA VLink IRQ number update
1256 if (via_vlink_dev_lo == -1)
1259 new_irq = dev->irq;
1266 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1267 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1292 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1335 * DreamWorks-provided workaround for Dunord I-3000 problem
1343 struct resource *r = &dev->resource[1];
1345 r->flags |= IORESOURCE_UNSET;
1351 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1353 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1357 dev->transparent = 1;
1392 if (pdev->revision != 0x04) /* Only C0 requires this */
1406 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1417 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1437 pdev->class &= ~5;
1444 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1454 pdev->class &= ~5;
1463 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1479 * This was originally an Alpha-specific thing, but it really fits here.
1480 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1484 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1497 * becomes necessary to do this tweak in two steps -- the chosen trigger
1498 * is either the Host bridge (preferred) or on-board VGA controller.
1511 * the DSDT and double-check that there is no code accessing the SMBus.
1517 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1518 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1519 switch (dev->subsystem_device) {
1520 case 0x8025: /* P4B-LX */
1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1527 switch (dev->subsystem_device) {
1528 case 0x80b1: /* P4GE-V */
1530 case 0x8093: /* P4B533-V */
1533 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1534 switch (dev->subsystem_device) {
1538 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1539 switch (dev->subsystem_device) {
1543 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1544 switch (dev->subsystem_device) {
1545 case 0x80c9: /* PU-DLS */
1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1549 switch (dev->subsystem_device) {
1555 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1556 switch (dev->subsystem_device) {
1561 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1562 switch (dev->subsystem_device) {
1563 case 0x80f2: /* P4P800-X */
1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1567 switch (dev->subsystem_device) {
1572 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1573 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1574 switch (dev->subsystem_device) {
1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1580 switch (dev->subsystem_device) {
1586 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1587 switch (dev->subsystem_device) {
1591 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1592 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1593 switch (dev->subsystem_device) {
1597 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1598 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1599 switch (dev->subsystem_device) {
1603 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1604 switch (dev->subsystem_device) {
1605 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1608 * its on-board VGA controller */
1611 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1612 switch (dev->subsystem_device) {
1617 * subvendor/subdevice IDs and on-board VGA
1623 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1624 switch (dev->subsystem_device) {
1628 * its on-board VGA controller */
1780 dev->device = devid;
1790 * -- bjd
1797 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1798 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1831 if (PCI_FUNC(pdev->devfn))
1837 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1840 switch (pdev->device) {
1872 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK;
1873 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr);
1876 pdev->class = class >> 8;
1901 if (dev->multifunction) {
1902 device_disable_async_suspend(&dev->dev);
1903 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1916 if ((pdev->class >> 8) != 0xff00)
1920 * The first BAR is the location of the IO-APIC... we must
1925 insert_resource(&iomem_resource, &pdev->resource[0]);
1932 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1940 dev->no_msi = 1;
1951 pdev->no_msi = 1;
1962 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1965 * break the PCI requirement for free-flowing writes and may lead to
1967 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1974 PROPERTY_ENTRY_BOOL("dma-can-stall"),
1978 if (pdev->revision != 0x21 && pdev->revision != 0x30)
1981 pdev->pasid_no_tlp = 1;
1984 * Set the dma-can-stall property on ACPI platforms. Device tree
1987 if (!pdev->dev.of_node &&
1988 device_create_managed_software_node(&pdev->dev, properties, NULL))
2000 * together on certain PXH-based systems.
2004 dev->no_msi = 1;
2020 dev->no_d1d2 = 1;
2046 if (dev->d3hot_delay >= delay)
2049 dev->d3hot_delay = delay;
2050 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
2051 dev->d3hot_delay);
2056 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
2057 dev->subsystem_device == 0x00e2)
2063 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2081 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2096 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
2107 .ident = "ASUSTek Computer INC. M2N-LR",
2110 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2128 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
2130 dev->vendor, dev->device);
2155 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2156 * 300641-004US, section 5.7.3.
2158 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2159 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2160 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2161 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2162 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2163 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2164 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2165 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2182 switch (dev->device) {
2193 case 0x6f28: /* Xeon D-1500 */
2205 dev->vendor, dev->device);
2208 * Device 29 Func 5 Device IDs of IO-APIC
2244 /* Disable boot interrupts on HT-1000 */
2270 dev->vendor, dev->device);
2279 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2293 if ((dev->revision == AMD_813X_REV_B1) ||
2294 (dev->revision == AMD_813X_REV_B2))
2302 dev->vendor, dev->device);
2321 dev->vendor, dev->device);
2326 dev->vendor, dev->device);
2333 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2335 * Re-allocate the region if needed...
2339 struct resource *r = &dev->resource[0];
2341 if (r->start & 0x8) {
2342 r->flags |= IORESOURCE_UNSET;
2355 * Re-allocate the regions to a 256-byte boundary if necessary.
2362 if (dev->revision >= 2)
2367 struct resource *r = &dev->resource[bar];
2368 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2370 r->flags |= IORESOURCE_UNSET;
2390 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2391 unsigned int num_serial = dev->subsystem_device & 0xf;
2403 switch (dev->device) {
2406 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2407 dev->subsystem_device == 0x0299)
2416 dev->device, num_parallel, num_serial);
2417 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2418 (dev->class & 0xff);
2431 switch (dev->device) {
2456 * re-enable them when it's ready.
2467 if (dev->pm_cap) {
2468 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2522 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2529 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2538 dev->clear_retrain_link = 1;
2547 u32 class = dev->class;
2556 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2557 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2558 class, dev->class);
2571 dev->io_window_1k = 1;
2605 * VT6212L is found -- the CX700 core itself also contains a USB
2615 * p should contain the first (internal) VT6212L -- see if we have
2637 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2669 * DRBs - this is where we expose device 6.
2670 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2712 if (dev->subordinate) {
2714 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2731 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2733 if (apc_bridge->device == 0x9602)
2750 while (pos && ttl--) {
2788 pdev = pci_get_slot(dev->bus, 0);
2804 while (pos && ttl--) {
2825 * The P5N32-SLI motherboards from Asus have a problem with MSI
2834 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2835 strstr(board_name, "P5N32-E SLI"))) {
2836 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2837 dev->no_msi = 1;
2845 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2850 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2855 dev->no_msi = 1;
2945 while (pos && ttl--) {
2973 dev_no = host_bridge->devfn >> 3;
2975 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
3031 dev_no = dev->devfn >> 3;
3032 for (i = dev_no; i >= 0; i--) {
3033 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
3068 while (pos && ttl--) {
3101 * a non-HyperTransport host bridge. Locate the host bridge.
3103 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
3150 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3167 if ((p->revision < 0x3B) && (p->revision >= 0x30))
3168 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3175 if (dev->revision < 0x18) {
3177 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3241 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3245 * tested), since currently there is no standard way to disable only MSI-X.
3252 dev->no_msi = 1;
3253 pci_warn(dev, "Disabling MSI/MSI-X\n");
3261 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3268 dev->is_hotplug_bridge = 1;
3285 * MMC controller - so the SDHCI driver never sees them.
3309 if (PCI_FUNC(dev->devfn))
3340 if (PCI_FUNC(dev->devfn))
3347 * 0x150 - SD2.0 mode enable for changing base clock
3349 * 0xe1 - Base clock frequency
3350 * 0x32 - 50Mhz new clock frequency
3351 * 0xf9 - Key register for 0x150
3352 * 0xfc - key register for 0xe1
3354 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3355 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3392 * This is a quirk for masking VT-d spec-defined errors to platform error
3395 * on the RAS config settings of the platform) when a VT-d fault happens.
3398 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3414 u32 class = dev->class;
3417 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3418 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3419 class, dev->class);
3430 dev->pcie_mpss = 1; /* 256 bytes */
3445 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3481 /* Intel 5000 series memory controllers and ports 2-7 */
3496 /* Intel 5100 series memory controllers and ports 2-7 */
3523 resource_set_size(&dev->resource[2], (resource_size_t)1 << val);
3529 resource_set_size(&dev->resource[4], (resource_size_t)1 << val);
3538 * and the interrupt ends up -somewhere-.
3578 dev->d3hot_delay = 0;
3584 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3614 dev->broken_intx_masking = 1;
3629 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3635 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3636 * DisINTx can be set but the interrupt status bit is non-functional.
3676 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3677 * If so, don't mark it as broken.
3692 if (pdev->device == mellanox_broken_intx_devs[i]) {
3693 pdev->broken_intx_masking = 1;
3699 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3702 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3705 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3706 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3709 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3717 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3729 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3730 fw_major, fw_minor, fw_subminor, pdev->device ==
3732 pdev->broken_intx_masking = 1;
3745 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3754 if ((dev->device & 0xffc0) == 0x2340)
3762 * The device will throw a Link Down error on AER-capable systems and
3797 if (!pci_is_root_bus(dev->bus))
3798 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3802 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3803 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3813 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3814 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3826 * Thunderbolt controllers with broken MSI hotplug signaling:
3832 if (pdev->is_hotplug_bridge &&
3833 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3834 pdev->revision <= 1))
3835 pdev->no_msi = 1;
3882 bridge = ACPI_HANDLE(&dev->dev);
3913 * Following are device-specific reset methods which can be used to
3914 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3920 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3950 return -ENOMEM;
3981 /* Device-specific reset method for Chelsio T4-based adapters */
3988 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3989 * that we have no device-specific reset method.
3991 if ((dev->device & 0xf000) != 0x4000)
3992 return -ENOTTY;
4018 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
4019 * are disabled when an MSI-X interrupt message needs to be delivered.
4020 * So we briefly re-enable MSI-X interrupts for the duration of the
4022 * MSI-X state.
4024 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
4026 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
4049 * FLR where config space reads from the device return -1. We seem to be
4066 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
4068 return -ENOTTY;
4075 return -ENOTTY;
4154 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4166 return -ENOTTY;
4172 return -ENOTTY;
4229 * These device-specific reset methods are here rather than in a driver
4237 for (i = pci_dev_reset_methods; i->reset; i++) {
4238 if ((i->vendor == dev->vendor ||
4239 i->vendor == (u16)PCI_ANY_ID) &&
4240 (i->device == dev->device ||
4241 i->device == (u16)PCI_ANY_ID))
4242 return i->reset(dev, probe);
4245 return -ENOTTY;
4250 if (PCI_FUNC(dev->devfn) != 0)
4251 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4268 if (PCI_FUNC(dev->devfn) != 1)
4269 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4327 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4337 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4362 pci_add_dma_alias(dev, id->driver_data, 1);
4367 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4372 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4373 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4377 if (!pci_is_root_bus(pdev->bus) &&
4378 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4379 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4380 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4381 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4398 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4411 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4446 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4454 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4459 u32 class = pdev->class;
4462 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4463 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4464 class, pdev->class);
4482 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4569 * If a non-compliant device generates a completion with a different
4571 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4575 * If the non-compliant device generates completions with zero attributes
4597 dev_name(&pdev->dev));
4615 if ((pdev->device & 0xff00) == 0x5400)
4622 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4640 * AMD has indicated that the devices below do not support peer-to-peer
4643 * peer-to-peer between functions can claim to support a subset of ACS.
4671 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4672 return -ENODEV;
4677 return -ENODEV;
4686 return -ENODEV;
4695 switch (dev->device) {
4712 return -ENOTTY;
4729 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4739 * But the implementation could block peer-to-peer transactions between them
4740 * and provide ACS-like functionality.
4747 return -ENOTTY;
4753 switch (dev->device) {
4765 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4780 /* Lynxpoint-H PCH */
4783 /* Lynxpoint-LP PCH */
4802 /* Filter out a few obvious non-matches first */
4807 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4816 return -ENOTTY;
4818 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4826 * These QCOM Root Ports do provide ACS-like features to disable peer
4830 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4856 return -ENOTTY;
4860 * but do include ACS-like functionality. The hardware doesn't support
4861 * peer-to-peer transactions via the root port and each has a unique
4881 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4882 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4890 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4894 * 0xa290-0xa29f PCI Express Root port #{0-16}
4895 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4901 * August 2017, Revision 002, Document#: 334660-002)[6]
4904 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4906 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4908 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4909 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4910 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4911 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4912 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4913 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4914 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4921 switch (dev->device) {
4939 return -ENOTTY;
4941 pos = dev->acs_cap;
4943 return -ENOTTY;
4960 * in their ACS capability if they support peer-to-peer transactions.
4962 * perform peer-to-peer with other functions, allowing us to mask out
4974 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4975 * "Root-Complex Peer to Peer Considerations".
4978 return -ENOTTY;
4988 * they do not allow peer-to-peer transactions between Root Ports.
5000 * they do not allow peer-to-peer transactions between Root Ports.
5010 * multi-function devices, the hardware isolates the functions by
5011 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and
5019 switch (dev->device) {
5093 /* 82571 (Quads omitted due to non-ACS switch) */
5112 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5113 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5116 /* Cavium multi-function devices */
5120 /* APM X-Gene */
5131 /* Broadcom multi-function device */
5154 /* Zhaoxin multi-function devices */
5159 /* LX2xx0A : without security features + CAN-FD */
5163 /* LX2xx0C : security features + CAN-FD */
5175 /* LX2xx2A : without security features + CAN-FD */
5179 /* LX2xx2C : security features + CAN-FD */
5199 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5204 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5216 * or control to indicate their support here. Multi-function express
5217 * devices which do not allow internal peer-to-peer between functions,
5220 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5221 if ((i->vendor == dev->vendor ||
5222 i->vendor == (u16)PCI_ANY_ID) &&
5223 (i->device == dev->device ||
5224 i->device == (u16)PCI_ANY_ID)) {
5225 ret = i->acs_enabled(dev, acs_flags);
5231 return -ENOTTY;
5243 /* Backbone Peer Non-Posted Disable */
5263 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5266 return -EINVAL;
5271 return -ENOMEM;
5275 * therefore read-only. If both posted and non-posted peer cycles are
5323 * if dev->external_facing || dev->untrusted
5328 return -ENOTTY;
5337 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5350 return -ENOTTY;
5352 pos = dev->acs_cap;
5354 return -ENOTTY;
5364 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5380 return -ENOTTY;
5382 pos = dev->acs_cap;
5384 return -ENOTTY;
5420 if ((p->vendor == dev->vendor ||
5421 p->vendor == (u16)PCI_ANY_ID) &&
5422 (p->device == dev->device ||
5423 p->device == (u16)PCI_ANY_ID) &&
5424 p->enable_acs) {
5425 ret = p->enable_acs(dev);
5431 return -ENOTTY;
5441 if ((p->vendor == dev->vendor ||
5442 p->vendor == (u16)PCI_ANY_ID) &&
5443 (p->device == dev->device ||
5444 p->device == (u16)PCI_ANY_ID) &&
5445 p->disable_acs_redir) {
5446 ret = p->disable_acs_redir(dev);
5452 return -ENOTTY;
5470 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5490 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5503 pdev->pcie_cap = pos;
5505 pdev->pcie_flags_reg = reg16;
5507 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5509 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5512 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5522 state->cap.cap_nr = PCI_CAP_ID_EXP;
5523 state->cap.cap_extended = 0;
5524 state->cap.size = size;
5525 cap = (u16 *)&state->cap.data[0];
5533 hlist_add_head(&state->next, &pdev->saved_cap_space);
5550 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5563 if (dev->revision == 0x1)
5570 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5575 bridge->no_ext_tags = 1;
5578 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5593 pdev->ats_cap = 0;
5603 if (pdev->device == 0x15d8) {
5604 if (pdev->revision == 0xcf &&
5605 pdev->subsystem_vendor == 0xea50 &&
5606 (pdev->subsystem_device == 0xce19 ||
5607 pdev->subsystem_device == 0xcc10 ||
5608 pdev->subsystem_device == 0xcc08))
5642 if (pdev->revision < 0x20)
5660 pdev->no_msi = 1;
5665 * Although not allowed by the spec, some multi-function devices have
5678 if (PCI_FUNC(pdev->devfn) != consumer)
5681 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5682 pdev->bus->number,
5683 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5684 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5689 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5697 pm_runtime_allow(&pdev->dev);
5730 * Create device link for GPUs with integrated Type-C UCSI controller
5757 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5768 /* The GPU becomes a multi-function device when the HDA is enabled */
5770 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type);
5781 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5783 * Item #36 - Downstream port applies ACS Source Validation to Completions
5796 * write, so we do config reads until we receive a non-Config Request Retry
5807 struct pci_dev *bridge = bus->self;
5809 pos = bridge->acs_cap;
5821 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5825 /* Re-enable ACS_SV if it was previously enabled */
5865 partition = ioread8(&mmio_ntb->partition_id);
5867 partition_map = ioread32(&mmio_ntb->ep_map);
5868 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5883 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5900 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
6057 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
6058 pdev->subsystem_device != 0x222e ||
6101 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
6113 * 7.3.27, 7.3.29-7.3.31.
6119 dev->no_msi = 1;
6122 dev->pme_support = 0;
6129 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
6135 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6155 if (!pdev->acs_cap)
6157 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
6167 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
6191 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
6198 dev->rom_bar_overlap = 1;
6215 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
6218 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
6272 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG;
6318 pdev->d3cold_delay = 1000;
6328 if (!parent || !parent->aer_cap)
6334 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
6336 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);