pci/controller/pci-xgene.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
73 	return readl(port->csr_base + reg);
78 	writel(val, port->csr_base + reg);
86 static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)
91 		return (struct xgene_pcie *)(bus->sysdata);
93 	cfg = bus->sysdata;
94 	return (struct xgene_pcie *)(cfg->priv);
101 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
103 	struct xgene_pcie *port = pcie_bus_to_port(bus);
105 	if (bus->number >= (bus->primary + 1))
106 		return port->cfg_base + AXI_EP_CFG_ACCESS;
108 	return port->cfg_base;
112  * For Configuration request, RTDID register is used as Bus Number,
115 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
117 	struct xgene_pcie *port = pcie_bus_to_port(bus);
121 	b = bus->number;
125 	if (!pci_is_root_bus(bus))
134  * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
135  * the translation from PCI bus to native BUS.  Entire DDR region
141 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
143 	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
150 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
153 	if ((pci_is_root_bus(bus) && devfn != 0) ||
154 	    xgene_pcie_hide_rc_bars(bus, offset))
157 	xgene_pcie_set_rtdid_reg(bus, devfn);
158 	return xgene_pcie_get_cfg_base(bus) + offset;
161 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
164 	struct xgene_pcie *port = pcie_bus_to_port(bus);
167 	ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val);
174 	 * we read the Vendor and Device ID of a non-existent device, the
181 	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
186 		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
195 	struct device *dev = &adev->dev;
214 		return -EINVAL;
218 	*res = *entry->res;
225 	struct device *dev = cfg->parent;
233 		return -ENOMEM;
240 	port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
241 	if (IS_ERR(port->csr_base))
242 		return PTR_ERR(port->csr_base);
244 	port->cfg_base = cfg->win;
245 	port->version = ipversion;
247 	cfg->priv = port;
283 	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
311 	port->link_up = false;
314 		port->link_up = true;
323 	struct device *dev = port->dev;
326 	port->clk = clk_get(dev, NULL);
327 	if (IS_ERR(port->clk)) {
329 		return -ENODEV;
332 	rc = clk_prepare_enable(port->clk);
344 	struct device *dev = port->dev;
348 	port->csr_base = devm_pci_remap_cfg_resource(dev, res);
349 	if (IS_ERR(port->csr_base))
350 		return PTR_ERR(port->csr_base);
353 	port->cfg_base = devm_ioremap_resource(dev, res);
354 	if (IS_ERR(port->cfg_base))
355 		return PTR_ERR(port->cfg_base);
356 	port->cfg_addr = res->start;
365 	struct device *dev = port->dev;
380 		mask = ~(size - 1) | flag;
395 	u64 addr = port->cfg_addr;
406 	struct device *dev = port->dev;
408 	resource_list_for_each_entry(window, &bridge->windows) {
409 		struct resource *res = window->res;
417 						pci_pio_to_address(res->start),
418 						res->start - window->offset);
421 			if (res->flags & IORESOURCE_PREFETCH)
423 							res->start,
424 							res->start -
425 							window->offset);
428 							res->start,
429 							res->start -
430 							window->offset);
436 			return -EINVAL;
454  * X-Gene PCIe support maximum 3 inbound memory regions
474 	return -EINVAL;
478 				    struct of_pci_range *range, u8 *ib_reg_mask)
480 	void __iomem *cfg_base = port->cfg_base;
481 	struct device *dev = port->dev;
484 	u64 cpu_addr = range->cpu_addr;
485 	u64 pci_addr = range->pci_addr;
486 	u64 size = range->size;
487 	u64 mask = ~(size - 1) | EN_REG;
492 	region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
494 		dev_warn(dev, "invalid pcie dma-range config\n");
498 	if (range->flags & IORESOURCE_PREFETCH)
524 	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
529 	struct device_node *np = port->node;
530 	struct of_pci_range range;
532 	struct device *dev = port->dev;
536 		dev_err(dev, "missing dma-ranges property\n");
537 		return -EINVAL;
540 	/* Get the dma-ranges from DT */
541 	for_each_of_pci_range(&parser, &range) {
542 		u64 end = range.cpu_addr + range.size - 1;
544 		dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
545 			range.flags, range.cpu_addr, end, range.pci_addr);
546 		xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
562 	struct device *dev = port->dev;
581 	if (!port->link_up)
584 		dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
602 	np = of_find_compatible_node(NULL, NULL, "apm,xgene1-msi");
614 	struct device *dev = &pdev->dev;
615 	struct device_node *dn = dev->of_node;
621 		return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
626 		return -ENOMEM;
630 	port->node = of_node_get(dn);
631 	port->dev = dev;
632 	port->version = XGENE_PCIE_IP_VER_1;
646 	bridge->sysdata = port;
647 	bridge->ops = &xgene_pcie_ops;
653 	{.compatible = "apm,xgene-pcie",},
659 		.name = "xgene-pcie",