controller/dwc/pcie-qcom.c

277 	void __iomem *parf;			/* DT parf */
381 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
383 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +
398 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
400 		writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +
404 			writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +
406 			writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +
410 		writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);
411 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +
476 	writel(1, pcie->parf + PARF_PHY_CTRL);
521 	val = readl(pcie->parf + PARF_PHY_CTRL);
523 	writel(val, pcie->parf + PARF_PHY_CTRL);
534 		       pcie->parf + PARF_PCS_DEEMPH);
537 		       pcie->parf + PARF_PCS_SWING);
538 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
543 		val = readl(pcie->parf + PARF_PHY_CTRL);
546 		writel(val, pcie->parf + PARF_PHY_CTRL);
550 	val = readl(pcie->parf + PARF_PHY_REFCLK);
555 	writel(val, pcie->parf + PARF_PHY_REFCLK);
640 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
643 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
656 	val = readl(pcie->parf + PARF_LTSSM);
658 	writel(val, pcie->parf + PARF_LTSSM);
720 	val = readl(pcie->parf + PARF_PHY_CTRL);
722 	writel(val, pcie->parf + PARF_PHY_CTRL);
727 	val = readl(pcie->parf + PARF_SYS_CTRL);
729 	writel(val, pcie->parf + PARF_SYS_CTRL);
731 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
733 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
735 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
737 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
767 	res->resets[9].id = "parf";
906 	val = readl(pcie->parf + PARF_PHY_CTRL);
908 	writel(val, pcie->parf + PARF_PHY_CTRL);
915 		pcie->parf + PARF_SYS_CTRL);
916 	writel(0, pcie->parf + PARF_Q2A_FLUSH);
999 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1002 	val = readl(pcie->parf + PARF_PHY_CTRL);
1004 	writel(val, pcie->parf + PARF_PHY_CTRL);
1009 	val = readl(pcie->parf + PARF_SYS_CTRL);
1011 	writel(val, pcie->parf + PARF_SYS_CTRL);
1013 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1015 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1018 	val = readl(pcie->parf + PARF_PM_CTRL);
1020 	writel(val, pcie->parf + PARF_PM_CTRL);
1024 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
1026 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
1043 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
1087 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
1099 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1101 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1216 	val = readl(pcie->parf + PARF_PHY_CTRL);
1218 	writel(val, pcie->parf + PARF_PHY_CTRL);
1222 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1224 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1232 		pcie->parf + PARF_SYS_CTRL);
1234 	writel(0, pcie->parf + PARF_Q2A_FLUSH);
1250 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1924 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1925 	if (IS_ERR(pcie->parf)) {
1926 		ret = PTR_ERR(pcie->parf);