controller/dwc/pcie-qcom-ep.c

183  * @parf: Qualcomm PCIe specific PARF register base
205 	void __iomem *parf;
433 	val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
435 	writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
438 	val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
442 	writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
445 	writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
448 	val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
450 	writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
453 	val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
455 	writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
458 	val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
460 	writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
463 	val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
465 	writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
473 	val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
478 	writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
481 	val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
485 	writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
488 	val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
490 	writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
510 	writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
514 	writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
517 		val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK);
519 		writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
522 	val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK);
524 	writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK);
542 		       pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
543 	writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
546 	val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
548 	writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
553 	val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
555 	writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
559 				pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE);
594 	pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
595 	if (IS_ERR(pcie_ep->parf))
596 		return PTR_ERR(pcie_ep->parf);
693 	u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
696 	writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
709 		val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
711 		writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
717 			val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
719 			writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);