controller/dwc/pcie-designware.c

142 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
456 		dev_err(pci->dev, "Read ATU address failed\n");
476 		dev_err(pci->dev, "Write ATU address failed\n");
494 	 * bit in the Control register-1 of the ATU outbound region acts
502 	 * registers, the transactions going through ATU won't have TLP
532 			      const struct dw_pcie_ob_atu_cfg *atu)
534 	u64 parent_bus_addr = atu->parent_bus_addr;
538 	limit_addr = parent_bus_addr + atu->size - 1;
542 	    !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
546 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
548 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
551 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
554 		dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
557 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
558 			      lower_32_bits(atu->pci_addr));
559 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
560 			      upper_32_bits(atu->pci_addr));
562 	val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
568 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
571 	if (atu->type == PCIE_ATU_TYPE_MSG) {
573 		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
575 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
578 	 * Make sure ATU enable takes effect before any subsequent config
582 		val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
641 	 * Make sure ATU enable takes effect before any subsequent config
678 	 * Make sure ATU enable takes effect before any subsequent config