controller/cadence/pcie-cadence-host.c

249 					enum cdns_pcie_rp_bar bar,
256 	if (!rc->avail_ib_bar[bar])
259 	rc->avail_ib_bar[bar] = false;
265 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0);
266 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1);
268 	if (bar == RP_NO_BAR)
272 	value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
273 		   LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
274 		   LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
275 		   LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
276 		   LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
279 			value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
280 		value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
283 			value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
284 		value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
287 	value |= LM_RC_BAR_CFG_APERTURE(bar, aperture);
296 	enum cdns_pcie_rp_bar bar, sel_bar;
299 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
300 		if (!rc->avail_ib_bar[bar])
303 		if (size <= bar_max_size[bar]) {
305 				sel_bar = bar;
309 			if (bar_max_size[bar] < bar_max_size[sel_bar])
310 				sel_bar = bar;
320 	enum cdns_pcie_rp_bar bar, sel_bar;
323 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
324 		if (!rc->avail_ib_bar[bar])
327 		if (size >= bar_max_size[bar]) {
329 				sel_bar = bar;
333 			if (bar_max_size[bar] > bar_max_size[sel_bar])
334 				sel_bar = bar;
347 	enum cdns_pcie_rp_bar bar;
371 		bar = cdns_pcie_host_find_min_bar(rc, size);
372 		if (bar != RP_BAR_UNDEFINED) {
373 			ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr,
376 				dev_err(dev, "IB BAR: %d config failed\n", bar);
391 		bar = cdns_pcie_host_find_max_bar(rc, size);
392 		if (bar == RP_BAR_UNDEFINED) {
398 		winsize = bar_max_size[bar];
399 		ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize,
402 			dev_err(dev, "IB BAR: %d config failed\n", bar);
427 	enum cdns_pcie_rp_bar bar;
431 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
432 		if (rc->avail_ib_bar[bar])
435 		cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), 0);
436 		cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), 0);
438 		if (bar == RP_NO_BAR)
441 		value = ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
442 			  LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
443 			  LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
444 			  LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
445 			  LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
465 		of_property_read_u32(np, "cdns,no-bar-match-nbits",
637 	enum cdns_pcie_rp_bar bar;
671 	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
672 		rc->avail_ib_bar[bar] = true;