Lines Matching defs:path
135 static void _rfk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path)
139 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
140 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
141 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
145 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
148 dpk->bp[path][kidx].ther_dpk);
253 void _txck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool force,
256 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0);
261 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck);
262 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1);
266 void _rxck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool force,
271 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0);
276 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck);
277 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1);
294 rtw8852bx_adc_cfg(rtwdev, bw, path);
298 enum rtw89_rf_path path, u8 kpath)
342 enum rtw89_rf_path path, u8 kpath)
371 enum rtw89_rf_path path)
373 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
374 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
375 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
381 u8 path, dck_tune;
388 for (path = 0; path < RF_PATH_NUM_8852BT; path++) {
389 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
390 dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
392 if (rtwdev->is_tssi_mode[path])
394 R_P0_TSSI_TRK + (path << 13),
397 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
398 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
399 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
400 _set_rx_dck(rtwdev, phy, path);
401 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
402 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
404 if (rtwdev->is_tssi_mode[path])
406 R_P0_TSSI_TRK + (path << 13),
411 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
418 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
420 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
422 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
423 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
426 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
429 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
432 false, rtwdev, path, RR_RCKS, BIT(3));
434 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
439 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
440 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
443 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
531 void _dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
533 if (path == RF_PATH_A) {
543 void _dack_reload_by_path(struct rtw89_dev *rtwdev, u8 path, u8 index)
555 if (path == RF_PATH_A)
570 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
579 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
588 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
597 tmp |= dack->msbk_d[path][index][i] << (i * 8);
604 tmp = (dack->biask_d[path][index] << 22) |
605 (dack->dadck_d[path][index] << 14);
616 void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
621 _dack_reload_by_path(rtwdev, path, i);
924 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
953 u8 path, u8 ktype)
961 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
964 iqk_cmd = 0x108 | (1 << (4 + path));
967 iqk_cmd = 0x208 | (1 << (4 + path));
970 iqk_cmd = 0x308 | (1 << (4 + path));
973 iqk_cmd = 0x008 | (1 << (path + 4)) |
974 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
977 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
980 iqk_cmd = 0x008 | (1 << (path + 4)) |
981 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
984 iqk_cmd = 0x408 | (1 << (4 + path));
987 iqk_cmd = 0x608 | (1 << (4 + path));
997 fail = _iqk_check_cal(rtwdev, path, ktype);
1002 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1006 switch (iqk_info->iqk_band[path]) {
1008 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1009 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
1010 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1011 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1012 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1013 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00);
1014 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1015 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1016 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x5);
1020 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1);
1021 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1022 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1023 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80);
1024 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1025 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1026 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4);
1034 static bool _iqk_2g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1038 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1040 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09);
1042 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4));
1044 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE);
1048 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1050 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24);
1051 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4));
1053 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER);
1057 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1059 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09);
1060 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4));
1062 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE);
1066 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1068 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24);
1069 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4));
1071 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER);
1079 static bool _iqk_5g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1083 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1085 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09);
1087 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4));
1089 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE);
1093 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1095 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24);
1096 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4));
1098 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER);
1102 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1104 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09);
1105 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4));
1107 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE);
1111 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1113 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24);
1114 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4));
1116 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER);
1123 static bool _iqk_2g_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1137 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1139 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1141 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1143 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1145 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1147 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1149 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1153 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1155 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1156 iqk_info->nb_txcfir[path] =
1157 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1162 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1164 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1169 path, gp, 1 << path, iqk_info->nb_txcfir[path]);
1176 iqk_info->nb_txcfir[path] = 0x40000002;
1177 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1184 static bool _iqk_5g_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1196 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
1197 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
1198 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
1200 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1202 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1204 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1206 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1208 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1212 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1215 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1216 iqk_info->nb_txcfir[path] =
1217 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1222 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1224 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1229 path, gp, 1 << path, iqk_info->nb_txcfir[path]);
1236 iqk_info->nb_txcfir[path] = 0x40000002;
1237 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1245 enum rtw89_phy_idx phy_idx, u8 path)
1252 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
1259 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1310 static bool _iqk_2g_rx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1325 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
1326 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
1327 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1328 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18);
1331 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
1332 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, g_idxattc2[gp]);
1333 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, g_idxattc1[gp]);
1335 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1337 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1339 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1341 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1345 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1351 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
1353 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, rf rxbb = %x\n", path,
1354 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0));
1356 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1362 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
1363 iqk_info->nb_rxcfir[path] =
1364 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1367 "[IQK]S%x, gp = 0x%x, 0x8%x3c = 0x%x\n", path,
1368 g_idx[gp], 1 << path, iqk_info->nb_rxcfir[path]);
1377 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
1386 iqk_info->nb_txcfir[path] = 0x40000002;
1387 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1390 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
1395 static bool _iqk_5g_rx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1410 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
1411 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
1412 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1413 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18);
1416 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, a_idxrxgain[gp]);
1417 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, a_idxattc2[gp]);
1418 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, a_idxattc1[gp]);
1420 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1422 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1424 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1426 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1430 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1436 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
1438 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, rf rxbb = %x\n", path,
1439 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0));
1441 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1445 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
1446 iqk_info->nb_rxcfir[path] =
1447 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1451 path, a_idx[gp], 1 << path, iqk_info->nb_rxcfir[path]);
1459 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
1468 iqk_info->nb_txcfir[path] = 0x40000002;
1469 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1472 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
1477 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1486 _iqk_txk_setting(rtwdev, path);
1487 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1488 lok_result = _iqk_2g_lok(rtwdev, phy_idx, path);
1490 lok_result = _iqk_5g_lok(rtwdev, phy_idx, path);
1499 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1500 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1501 rtw89_write_rf(rtwdev, path, RR_LOKVB, RFREG_MASK, 0x80200);
1505 rtw89_read_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK));
1507 rtw89_read_rf(rtwdev, path, RR_RSV2, RFREG_MASK));
1509 rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK));
1511 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1512 txk_result = _iqk_2g_tx(rtwdev, phy_idx, path);
1514 txk_result = _iqk_5g_tx(rtwdev, phy_idx, path);
1516 _iqk_rxclk_setting(rtwdev, path);
1517 _iqk_adc_fifo_rst(rtwdev, phy_idx, path);
1519 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1520 rxk_result = _iqk_2g_rx(rtwdev, phy_idx, path);
1522 rxk_result = _iqk_5g_rx(rtwdev, phy_idx, path);
1529 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,
1539 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1542 iqk_info->iqk_band[path] = chan->band_type;
1543 iqk_info->iqk_bw[path] = chan->band_width;
1544 iqk_info->iqk_ch[path] = chan->channel;
1545 iqk_info->iqk_mcc_ch[idx][path] = chan->channel;
1546 iqk_info->iqk_table_idx[path] = idx;
1549 path, reg_rf18, idx);
1551 path, reg_rf18);
1553 path, reg_35c);
1557 idx, path, iqk_info->iqk_mcc_ch[idx][path]);
1560 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1562 _iqk_by_path(rtwdev, phy_idx, path);
1565 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1572 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1573 MASKDWORD, iqk_info->nb_txcfir[path]);
1574 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1575 MASKDWORD, iqk_info->nb_rxcfir[path]);
1577 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1579 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1583 0x00000e19 + (path << 4));
1585 _iqk_check_cal(rtwdev, path, 0x0);
1593 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), BIT(28), 0x0);
1595 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1596 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1597 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3);
1598 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1599 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
1603 enum rtw89_phy_idx phy_idx, u8 path)
1627 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1632 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), 0x00000001, idx);
1633 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 0x00000008, idx);
1634 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
1635 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000000);
1637 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1638 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
1644 enum rtw89_phy_idx phy_idx, u8 path)
1689 u8 idx, path;
1707 for (path = 0; path < RTW8852BT_SS; path++) {
1708 iqk_info->lok_cor_fail[idx][path] = false;
1709 iqk_info->lok_fin_fail[idx][path] = false;
1710 iqk_info->iqk_tx_fail[idx][path] = false;
1711 iqk_info->iqk_rx_fail[idx][path] = false;
1712 iqk_info->iqk_mcc_ch[idx][path] = 0x0;
1713 iqk_info->iqk_table_idx[path] = 0x0;
1721 u8 path;
1724 for (path = 0; path < RF_PATH_MAX; path++) {
1725 if (!(kpath & BIT(path)))
1730 rtwdev, path, RR_MOD, RR_MOD_MASK);
1732 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret);
1746 enum rtw89_phy_idx phy_idx, u8 path,
1762 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1765 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
1766 _iqk_macbb_setting(rtwdev, phy_idx, path);
1767 _iqk_preset(rtwdev, path);
1768 _iqk_start_iqk(rtwdev, phy_idx, path);
1769 _iqk_restore(rtwdev, path);
1770 _iqk_afebb_restore(rtwdev, phy_idx, path);
1772 _rfk_reload_rf_reg(rtwdev, backup_rf_val[path], path);
1798 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off)
1801 u8 val, kidx = dpk->cur_idx[path];
1804 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
1811 val = dpk->is_dpk_enable & off_reverse & dpk->bp[path][kidx].path_ok;
1813 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1816 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1821 enum rtw89_rf_path path, enum rtw8852bt_dpk_id id)
1827 dpk_cmd = (id << 8) | (0x19 + (path << 4));
1861 enum rtw89_rf_path path)
1863 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1864 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1868 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d RXDCK\n", path);
1872 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1877 u8 kidx = dpk->cur_idx[path];
1879 dpk->bp[path][kidx].band = chan->band_type;
1880 dpk->bp[path][kidx].ch = chan->channel;
1881 dpk->bp[path][kidx].bw = chan->band_width;
1885 path, dpk->cur_idx[path], phy,
1886 rtwdev->is_tssi_mode[path] ? "on" : "off",
1888 dpk->bp[path][kidx].band == 0 ? "2G" :
1889 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1890 dpk->bp[path][kidx].ch,
1891 dpk->bp[path][kidx].bw == 0 ? "20M" :
1892 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1896 enum rtw89_rf_path path, bool is_pause)
1898 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1901 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1906 enum rtw89_rf_path path)
1912 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8),
1915 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1919 enum rtw89_rf_path path, u8 cur_rxbb, u32 rf_18)
1922 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0);
1924 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18);
1925 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd);
1926 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
1929 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13);
1931 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00);
1933 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05);
1935 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0);
1936 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1937 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014);
1944 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
1948 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
1951 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
1952 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5);
1956 enum rtw89_rf_path path, u8 kidx)
1960 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
1961 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1962 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2);
1963 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1964 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1966 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1967 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5);
1968 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1969 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1970 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC);
1971 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0);
1972 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800);
1975 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
1976 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
1977 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
1981 enum rtw89_rf_path path, bool is_bypass)
1984 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1986 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1989 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1991 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1997 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2001 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2003 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
2009 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2010 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2014 enum rtw89_rf_path path, u8 kidx, u8 gain)
2019 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
2025 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2043 path, corr_idx, corr_val);
2045 dpk->corr_idx[path][kidx] = corr_idx;
2046 dpk->corr_val[path][kidx] = corr_val;
2058 path, dc_i, dc_q);
2060 dpk->dc_i[path][kidx] = dc_i;
2061 dpk->dc_q[path][kidx] = dc_q;
2071 enum rtw89_rf_path path, u8 kidx)
2073 _dpk_one_shot(rtwdev, phy, path, SYNC);
2146 enum rtw89_rf_path path, u8 kidx)
2148 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS);
2155 enum rtw89_rf_path path, u8 kidx)
2157 _dpk_tpg_sel(rtwdev, path, kidx);
2158 _dpk_one_shot(rtwdev, phy, path, KIP_PRESET);
2162 enum rtw89_rf_path path)
2166 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
2172 u8 _dpk_txagc_check_8852bt(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 txagc)
2176 if (txagc >= dpk->max_dpk_txagc[path])
2177 txagc = dpk->max_dpk_txagc[path];
2185 enum rtw89_rf_path path, u8 txagc)
2189 val = _dpk_txagc_check_8852bt(rtwdev, path, txagc);
2190 rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, val);
2192 _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC);
2199 enum rtw89_rf_path path)
2203 _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC);
2208 enum rtw89_rf_path path, u8 txagc, s8 gain_offset)
2210 txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK);
2219 _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2226 static bool _dpk_pas_read(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
2269 enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
2284 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
2285 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
2290 _dpk_sync(rtwdev, phy, path, kidx);
2293 _dpk_bypass_rxcfir(rtwdev, path, true);
2295 _dpk_lbk_rxiqk(rtwdev, phy, path,
2299 if (_dpk_sync_check(rtwdev, path, kidx) == true) {
2314 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
2326 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB, tmp_rxbb);
2331 _dpk_lbk_rxiqk(rtwdev, phy, path, tmp_rxbb, rf_18);
2340 _dpk_gainloss(rtwdev, phy, path, kidx);
2344 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, path, true)) ||
2356 tmp_txagc == dpk->max_dpk_txagc[path]) {
2361 tmp_txagc = _dpk_set_offset(rtwdev, phy, path,
2369 if (tmp_txagc == 0x3f || tmp_txagc == dpk->max_dpk_txagc[path]) {
2374 tmp_txagc = _dpk_set_offset(rtwdev, phy, path,
2382 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_txagc,
2395 _dpk_pas_read(rtwdev, path, false);
2404 enum rtw89_rf_path path, u8 order)
2413 dpk->dpk_order[path] = 0x3;
2419 dpk->dpk_order[path] = 0x1;
2425 dpk->dpk_order[path] = 0x0;
2442 enum rtw89_rf_path path, u8 kidx, u8 gain)
2446 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
2447 dpk->bp[path][kidx].band == RTW89_BAND_5G)
2448 _dpk_set_mdpd_para(rtwdev, path, 0x2);
2450 _dpk_set_mdpd_para(rtwdev, path, 0x0);
2452 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL);
2456 enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc)
2462 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), BIT(8), kidx);
2468 dpk->bp[path][kidx].txagc_dpk = txagc;
2469 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
2472 dpk->bp[path][kidx].pwsf = pwsf;
2473 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2476 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2477 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2479 dpk->bp[path][kidx].gs = gs;
2482 R_DPD_CH0A + (path << 8) + (kidx << 2),
2486 R_DPD_CH0A + (path << 8) + (kidx << 2),
2489 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2490 B_DPD_ORDER_V1, dpk->dpk_order[path]);
2492 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0);
2497 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
2508 if (cur_band != dpk->bp[path][idx].band ||
2509 cur_ch != dpk->bp[path][idx].ch)
2512 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2514 dpk->cur_idx[path] = idx;
2517 "[DPK] reload S%d[%d] success\n", path, idx);
2524 void _rf_direct_cntrl(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool is_bybb)
2527 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
2529 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
2533 void _drf_direct_cntrl(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool is_bybb)
2536 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
2538 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
2542 enum rtw89_rf_path path, u8 gain,
2546 u8 txagc = 0x38, kidx = dpk->cur_idx[path];
2550 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
2552 _rf_direct_cntrl(rtwdev, path, false);
2553 _drf_direct_cntrl(rtwdev, path, false);
2555 _dpk_kip_pwr_clk_on(rtwdev, path);
2556 _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2557 _dpk_rf_setting(rtwdev, gain, path, kidx);
2558 _dpk_rx_dck(rtwdev, phy, path);
2559 _dpk_kip_preset(rtwdev, phy, path, kidx);
2560 _dpk_kip_set_rxagc(rtwdev, phy, path);
2561 _dpk_table_select(rtwdev, path, kidx, gain);
2563 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx);
2565 _rfk_get_thermal(rtwdev, kidx, path);
2572 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain);
2574 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, RF_RX);
2575 _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc);
2579 dpk->bp[path][kidx].path_ok = 1;
2581 dpk->bp[path][kidx].path_ok = 0;
2583 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2586 _dpk_onoff(rtwdev, path, is_fail);
2588 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2603 u8 path;
2605 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) {
2606 reloaded[path] = _dpk_reload_check(rtwdev, phy, path, chanctx_idx);
2607 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2608 dpk->cur_idx[path] = !dpk->cur_idx[path];
2610 _dpk_onoff(rtwdev, path, false);
2616 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) {
2617 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
2618 _dpk_information(rtwdev, phy, path, chanctx_idx);
2619 if (rtwdev->is_tssi_mode[path])
2620 _dpk_tssi_pause(rtwdev, path, true);
2623 _rfk_bb_afe_setting(rtwdev, phy, path, kpath);
2625 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++)
2626 _dpk_main(rtwdev, phy, path, 1, chanctx_idx);
2628 _rfk_bb_afe_restore(rtwdev, phy, path, kpath);
2630 _dpk_kip_restore(rtwdev, path);
2634 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) {
2635 _rfk_reload_rf_reg(rtwdev, backup_rf_val[path], path);
2636 if (rtwdev->is_tssi_mode[path])
2637 _dpk_tssi_pause(rtwdev, path, false);
2666 u8 path, kpath;
2670 for (path = 0; path < RTW8852BT_SS; path++) {
2671 if (kpath & BIT(path))
2672 _dpk_onoff(rtwdev, path, true);
2682 u8 path, kidx;
2687 for (path = 0; path < RF_PATH_NUM_8852BT; path++) {
2688 kidx = dpk->cur_idx[path];
2692 path, kidx, dpk->bp[path][kidx].ch);
2694 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2699 if (dpk->bp[path][kidx].ch && cur_ther)
2700 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
2702 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2703 delta_ther[path] = delta_ther[path] * 3 / 2;
2705 delta_ther[path] = delta_ther[path] * 5 / 2;
2707 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2710 if (rtwdev->is_tssi_mode[path]) {
2711 trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
2718 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2721 rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13),
2729 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2734 txagc_ofst, delta_ther[path]);
2735 tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
2744 ini_diff = txagc_ofst + (delta_ther[path]);
2747 R_P0_TXDPD + (path << 13),
2750 pwsf[0] = dpk->bp[path][kidx].pwsf +
2752 pwsf[1] = dpk->bp[path][kidx].pwsf +
2755 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff;
2756 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff;
2759 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2760 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2770 R_DPD_BND + (path << 8) + (kidx << 2),
2773 R_DPD_BND + (path << 8) + (kidx << 2),
2782 u8 tx_scale, ofdm_bkof, path, kpath;
2792 for (path = 0; path < RF_PATH_NUM_8852BT; path++) {
2793 if (!(kpath & BIT(path)))
2796 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8),
2799 "[RFK] Set S%d DPD backoff to 0dB\n", path);
2813 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2818 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2820 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2824 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2835 if (path == RF_PATH_A)
2847 enum rtw89_rf_path path)
2849 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2856 enum rtw89_rf_path path)
2858 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2864 enum rtw89_rf_path path)
2866 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2872 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2926 if (path == RF_PATH_A) {
3032 enum rtw89_rf_path path)
3034 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3040 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3044 if (path == RF_PATH_A)
3055 enum rtw89_rf_path path, bool all,
3062 if (path == RF_PATH_A) {
3087 enum rtw89_rf_path path)
3089 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3095 enum rtw89_rf_path path)
3097 if (path == RF_PATH_A)
3105 enum rtw89_rf_path path)
3107 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__,
3108 path);
3110 if (path == RF_PATH_A)
3302 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3314 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
3319 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3320 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3324 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3325 path, val, de_1st, de_2nd);
3327 val = tssi_info->tssi_mcs[path][gidx];
3330 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3337 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3349 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3350 path, tgidx);
3355 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3356 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3360 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3361 path, val, tde_1st, tde_2nd);
3363 val = tssi_info->tssi_trim[path][tgidx];
3366 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3367 path, val);
3393 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3410 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3429 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
3434 R_TSSI_PA_K1 + (path << 13),
3435 rtw89_phy_read32(rtwdev, R_TSSI_PA_K1 + (path << 13)),
3436 R_TSSI_PA_K2 + (path << 13),
3437 rtw89_phy_read32(rtwdev, R_TSSI_PA_K2 + (path << 13)),
3438 R_P0_TSSI_ALIM1 + (path << 13),
3439 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM1 + (path << 13)),
3440 R_P0_TSSI_ALIM3 + (path << 13),
3441 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM3 + (path << 13)),
3442 R_TSSI_PA_K5 + (path << 13),
3443 rtw89_phy_read32(rtwdev, R_TSSI_PA_K5 + (path << 13)),
3444 R_P0_TSSI_ALIM2 + (path << 13),
3445 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM2 + (path << 13)),
3446 R_P0_TSSI_ALIM4 + (path << 13),
3447 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM4 + (path << 13)),
3448 R_TSSI_PA_K8 + (path << 13),
3449 rtw89_phy_read32(rtwdev, R_TSSI_PA_K8 + (path << 13)));
3453 enum rtw89_phy_idx phy, enum rtw89_rf_path path,
3461 "======>%s phy=%d path=%d\n", __func__, phy, path);
3474 if (tssi_info->alignment_done[path][band]) {
3475 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3476 tssi_info->alignment_value[path][band][0]);
3477 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3478 tssi_info->alignment_value[path][band][1]);
3479 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3480 tssi_info->alignment_value[path][band][2]);
3481 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3482 tssi_info->alignment_value[path][band][3]);
3485 _tssi_alimentk_dump_result(rtwdev, path);
3489 enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm,
3494 if (path == RF_PATH_A)
3496 else if (path == RF_PATH_B)
3498 else if (path == RF_PATH_AB)
3501 rx_path = RF_ABCD; /* don't change path, but still set others */
3505 rtw8852bx_bb_cfg_tx_path(rtwdev, path);
3563 enum rtw89_rf_path path, const s16 *power,
3572 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0);
3573 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1);
3577 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD);
3579 "[TSSI PA K] 0x%x = 0x%08x path=%d\n",
3580 _tssi_trigger[path], tmp, path);
3583 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true,
3593 "[TSSI PA K] First HWTXcounter=%d path=%d\n",
3594 tx_counter_tmp, path);
3597 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
3609 "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n",
3610 k, tx_counter_tmp, path);
3615 "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n",
3616 k, path);
3618 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3623 rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
3626 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3632 "[TSSI PA K] Final HWTXcounter=%d path=%d\n",
3633 tx_counter_tmp, path);
3640 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3663 "======> %s channel=%d path=%d\n", __func__, channel,
3664 path);
3693 ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt, chan);
3703 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1],
3710 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2],
3715 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3],
3720 if (path == RF_PATH_A) {
3750 tssi_info->alignment_done[path][band] = true;
3751 tssi_info->alignment_value[path][band][0] =
3752 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3753 tssi_info->alignment_value[path][band][1] =
3754 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3755 tssi_info->alignment_value[path][band][2] =
3756 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3757 tssi_info->alignment_value[path][band][3] =
3758 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3760 tssi_info->check_backup_aligmk[path][ch_idx] = true;
3761 tssi_info->alignment_backup_by_ch[path][ch_idx][0] =
3762 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3763 tssi_info->alignment_backup_by_ch[path][ch_idx][1] =
3764 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3765 tssi_info->alignment_backup_by_ch[path][ch_idx][2] =
3766 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3767 tssi_info->alignment_backup_by_ch[path][ch_idx][3] =
3768 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3771 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
3772 path, band, R_P0_TSSI_ALIM1 + (path << 13),
3773 tssi_info->alignment_value[path][band][0]);
3775 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
3776 path, band, R_P0_TSSI_ALIM3 + (path << 13),
3777 tssi_info->alignment_value[path][band][1]);
3779 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
3780 path, band, R_P0_TSSI_ALIM2 + (path << 13),
3781 tssi_info->alignment_value[path][band][2]);
3783 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n",
3784 path, band, R_P0_TSSI_ALIM4 + (path << 13),
3785 tssi_info->alignment_value[path][band][3]);
3805 u8 path;
3807 for (path = 0; path < 2; path++) {
3808 dpk->cur_idx[path] = 0;
3809 dpk->max_dpk_txagc[path] = 0x3F;
3819 u8 path;
3821 for (path = 0; path < RF_PATH_NUM_8852BT; path++)
3822 _rck(rtwdev, path);
4017 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
4025 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
4028 "[RFK]Invalid RF_0x18 for Path-%d\n", path);
4052 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
4054 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
4055 bw, path, reg18_addr,
4056 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
4146 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
4155 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
4168 if (path == RF_PATH_A && dav)
4171 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
4173 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
4174 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
4178 central_ch, path, reg18_addr,
4179 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
4191 enum rtw89_rf_path path)
4193 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
4194 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
4197 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
4199 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
4201 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
4203 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
4206 path, rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
4208 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4214 u8 kpath, path;
4218 for (path = 0; path < RF_PATH_NUM_8852BT; path++) {
4219 if (!(kpath & BIT(path)))
4222 _set_rxbb_bw(rtwdev, bw, path);
4270 u8 path;
4275 for (path = 0; path < RTW8852BT_SS; path++)
4276 _dpk_onoff(rtwdev, path, false);
4280 for (path = 0; path < RTW8852BT_SS; path++)
4281 _dpk_onoff(rtwdev, path, false);