Lines Matching defs:path
236 enum rtw89_rf_path path, bool is_bybb)
239 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
241 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
245 enum rtw89_rf_path path, bool is_bybb)
248 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
250 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
253 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
270 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
272 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val);
296 enum rtw89_rf_path path)
298 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
299 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
300 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
306 u8 path, dck_tune;
313 for (path = 0; path < RF_PATH_NUM_8852B; path++) {
314 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
315 dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
317 if (rtwdev->is_tssi_mode[path])
319 R_P0_TSSI_TRK + (path << 13),
322 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
323 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
324 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
325 _set_rx_dck(rtwdev, phy, path);
326 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
327 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
329 if (rtwdev->is_tssi_mode[path])
331 R_P0_TSSI_TRK + (path << 13),
336 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
343 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
345 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
347 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
348 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
351 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
354 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
357 false, rtwdev, path, RR_RCKS, BIT(3));
359 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
364 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
365 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
368 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
488 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
494 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
508 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
588 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
590 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
594 _check_addc(rtwdev, path);
596 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
792 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
797 switch (iqk_info->iqk_band[path]) {
799 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
800 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
801 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
802 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
805 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
806 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
807 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
808 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
816 u8 path, u8 ktype)
825 iqk_cmd = 0x108 | (1 << (4 + path));
829 iqk_cmd = 0x208 | (1 << (4 + path));
833 iqk_cmd = 0x308 | (1 << (4 + path));
837 iqk_cmd = 0x008 | (1 << (path + 4)) |
838 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
841 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
845 iqk_cmd = 0x008 | (1 << (path + 4)) |
846 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
851 iqk_cmd = 0x408 | (1 << (4 + path));
856 iqk_cmd = 0x608 | (1 << (4 + path));
864 fail = _iqk_check_cal(rtwdev, path);
871 u8 path)
879 switch (iqk_info->iqk_band[path]) {
881 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
883 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
885 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
889 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
891 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
893 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
900 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
902 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
904 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
906 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
908 BIT(16 + gp + path * 4), fail);
911 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
914 iqk_info->nb_rxcfir[path] = 0x40000002;
915 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
917 iqk_info->is_wb_rxiqk[path] = false;
919 iqk_info->nb_rxcfir[path] = 0x40000000;
920 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
922 iqk_info->is_wb_rxiqk[path] = true;
929 u8 path)
936 switch (iqk_info->iqk_band[path]) {
938 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
940 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
942 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
946 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
948 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
950 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
957 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
958 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
959 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
960 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
963 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
964 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
966 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
969 iqk_info->nb_rxcfir[path] =
970 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2;
972 iqk_info->nb_rxcfir[path] = 0x40000002;
977 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
981 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1016 static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1024 switch (iqk_info->iqk_band[path]) {
1026 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1028 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1030 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1032 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1036 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1038 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1040 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1042 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1049 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1051 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1053 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1055 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1058 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1060 BIT(8 + gp + path * 4), fail);
1065 iqk_info->nb_txcfir[path] = 0x40000002;
1066 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1068 iqk_info->is_wb_txiqk[path] = false;
1070 iqk_info->nb_txcfir[path] = 0x40000000;
1071 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1073 iqk_info->is_wb_txiqk[path] = true;
1079 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1085 switch (iqk_info->iqk_band[path]) {
1087 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1089 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1091 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1093 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1097 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1099 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1101 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1103 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1110 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1111 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
1112 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
1113 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
1115 kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1118 iqk_info->nb_txcfir[path] =
1119 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1122 iqk_info->nb_txcfir[path] = 0x40000002;
1127 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
1132 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
1134 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
1135 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1136 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
1138 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
1139 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
1140 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1141 rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1);
1143 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path,
1144 rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK));
1147 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1159 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1168 iqk_info->lok_idac[ch][path] = tmp;
1170 tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
1179 iqk_info->lok_vbuf[ch][path] = tmp;
1182 "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path,
1183 iqk_info->lok_idac[ch][path]);
1185 "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path,
1186 iqk_info->lok_vbuf[ch][path]);
1191 static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1198 switch (iqk_info->iqk_band[path]) {
1200 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1201 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1204 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1205 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4);
1211 switch (iqk_info->iqk_band[path]) {
1213 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1216 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1222 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
1223 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE);
1224 iqk_info->lok_cor_fail[0][path] = tmp;
1226 switch (iqk_info->iqk_band[path]) {
1228 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1231 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1237 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
1238 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1240 switch (iqk_info->iqk_band[path]) {
1242 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1245 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1251 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
1253 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE);
1254 iqk_info->lok_fin_fail[0][path] = tmp;
1256 switch (iqk_info->iqk_band[path]) {
1258 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1261 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1267 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
1268 _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1270 return _lok_finetune_check(rtwdev, path);
1273 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1277 switch (iqk_info->iqk_band[path]) {
1279 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00);
1280 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1281 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
1282 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1283 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1284 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1285 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00);
1286 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1290 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
1291 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1);
1292 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1293 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1294 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80);
1295 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1303 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
1316 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1322 flag = iqk_info->lok_cor_fail[0][path];
1323 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
1324 flag = iqk_info->lok_fin_fail[0][path];
1325 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
1326 flag = iqk_info->iqk_tx_fail[0][path];
1327 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
1328 flag = iqk_info->iqk_rx_fail[0][path];
1329 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
1331 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1332 iqk_info->bp_iqkenable[path] = tmp;
1333 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1334 iqk_info->bp_txkresult[path] = tmp;
1335 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1336 iqk_info->bp_rxkresult[path] = tmp;
1340 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
1343 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
1347 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1355 _iqk_txclk_setting(rtwdev, path);
1359 _lok_res_table(rtwdev, path, ibias++);
1360 _iqk_txk_setting(rtwdev, path);
1361 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path);
1367 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path);
1371 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1373 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1376 _iqk_rxclk_setting(rtwdev, path);
1377 _iqk_rxk_setting(rtwdev, path);
1379 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1381 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1383 _iqk_info_iqk(rtwdev, phy_idx, path);
1386 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,
1396 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1399 iqk_info->iqk_band[path] = chan->band_type;
1400 iqk_info->iqk_bw[path] = chan->band_width;
1401 iqk_info->iqk_ch[path] = chan->channel;
1402 iqk_info->iqk_mcc_ch[idx][path] = chan->channel;
1403 iqk_info->iqk_table_idx[path] = idx;
1406 path, reg_rf18, idx);
1408 path, reg_rf18);
1412 idx, path, iqk_info->iqk_mcc_ch[idx][path]);
1420 "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path,
1425 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
1426 iqk_info->iqk_band[path]);
1428 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
1429 iqk_info->iqk_bw[path]);
1430 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
1431 iqk_info->iqk_ch[path]);
1434 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1436 _iqk_by_path(rtwdev, phy_idx, path);
1439 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1444 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1445 iqk_info->nb_txcfir[path]);
1446 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1447 iqk_info->nb_rxcfir[path]);
1449 0x00000e19 + (path << 4));
1450 fail = _iqk_check_cal(rtwdev, path);
1460 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1461 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1462 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3);
1463 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1464 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
1468 enum rtw89_phy_idx phy_idx, u8 path)
1493 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1500 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
1501 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
1503 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1504 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
1508 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path,
1509 rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD));
1510 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path,
1511 rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD));
1515 enum rtw89_phy_idx phy_idx, u8 path)
1541 u8 idx, path;
1558 for (path = 0; path < RTW8852B_IQK_SS; path++) {
1559 iqk_info->lok_cor_fail[idx][path] = false;
1560 iqk_info->lok_fin_fail[idx][path] = false;
1561 iqk_info->iqk_tx_fail[idx][path] = false;
1562 iqk_info->iqk_rx_fail[idx][path] = false;
1563 iqk_info->iqk_mcc_ch[idx][path] = 0x0;
1564 iqk_info->iqk_table_idx[path] = 0x0;
1572 u8 path;
1575 for (path = 0; path < RF_PATH_MAX; path++) {
1576 if (!(kpath & BIT(path)))
1581 rtwdev, path, RR_MOD, RR_MOD_MASK);
1583 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret);
1597 enum rtw89_phy_idx phy_idx, u8 path,
1613 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1616 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1617 _iqk_macbb_setting(rtwdev, phy_idx, path);
1618 _iqk_preset(rtwdev, path);
1619 _iqk_start_iqk(rtwdev, phy_idx, path);
1620 _iqk_restore(rtwdev, path);
1621 _iqk_afebb_restore(rtwdev, phy_idx, path);
1623 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1650 u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
1655 reg_bkup[path][i] =
1656 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1658 reg[i] + (path << 8), reg_bkup[path][i]);
1663 const u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
1668 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
1669 reg_bkup[path][i]);
1671 reg[i] + (path << 8), reg_bkup[path][i]);
1688 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off)
1691 u8 val, kidx = dpk->cur_idx[path];
1693 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
1695 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1698 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1703 enum rtw89_rf_path path, enum rtw8852b_dpk_id id)
1709 dpk_cmd = (id << 8) | (0x19 + (path << 4));
1745 enum rtw89_rf_path path)
1747 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
1748 _set_rx_dck(rtwdev, phy, path);
1752 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1757 u8 kidx = dpk->cur_idx[path];
1759 dpk->bp[path][kidx].band = chan->band_type;
1760 dpk->bp[path][kidx].ch = chan->channel;
1761 dpk->bp[path][kidx].bw = chan->band_width;
1765 path, dpk->cur_idx[path], phy,
1766 rtwdev->is_tssi_mode[path] ? "on" : "off",
1768 dpk->bp[path][kidx].band == 0 ? "2G" :
1769 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1770 dpk->bp[path][kidx].ch,
1771 dpk->bp[path][kidx].bw == 0 ? "20M" :
1772 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1777 enum rtw89_rf_path path, u8 kpath,
1795 enum rtw89_rf_path path, u8 kpath,
1812 enum rtw89_rf_path path, bool is_pause)
1814 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1817 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1822 enum rtw89_rf_path path)
1827 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1);
1829 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1833 enum rtw89_rf_path path)
1838 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
1841 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0);
1843 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1844 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
1845 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd);
1846 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
1849 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13);
1851 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00);
1853 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05);
1855 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0);
1856 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1857 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014);
1863 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
1865 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
1869 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
1872 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
1873 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5);
1876 static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path)
1880 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
1881 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
1882 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
1886 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
1889 dpk->bp[path][kidx].ther_dpk);
1893 enum rtw89_rf_path path, u8 kidx)
1897 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
1898 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1899 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2);
1900 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1901 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1903 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1904 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5);
1905 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1906 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1907 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC);
1908 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0);
1909 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800);
1912 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
1913 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
1914 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
1918 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
1919 rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK),
1920 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
1924 enum rtw89_rf_path path, bool is_bypass)
1927 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1929 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1932 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
1933 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1936 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
1937 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
1939 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
1940 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1946 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1950 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
1952 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
1958 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1959 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
1963 enum rtw89_rf_path path, u8 kidx, u8 gain)
1968 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
1974 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1990 path, corr_idx, corr_val);
1992 dpk->corr_idx[path][kidx] = corr_idx;
1993 dpk->corr_val[path][kidx] = corr_val;
2004 path, dc_i, dc_q);
2006 dpk->dc_i[path][kidx] = dc_i;
2007 dpk->dc_q[path][kidx] = dc_q;
2017 enum rtw89_rf_path path, u8 kidx)
2019 _dpk_one_shot(rtwdev, phy, path, SYNC);
2021 return _dpk_sync_check(rtwdev, path, kidx);
2094 enum rtw89_rf_path path, u8 kidx)
2096 _dpk_table_select(rtwdev, path, kidx, 1);
2097 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS);
2101 enum rtw89_rf_path path, u8 kidx)
2103 _dpk_tpg_sel(rtwdev, path, kidx);
2104 _dpk_one_shot(rtwdev, phy, path, KIP_PRESET);
2108 enum rtw89_rf_path path)
2112 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
2118 enum rtw89_rf_path path, u8 txagc)
2120 rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc);
2122 _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC);
2129 enum rtw89_rf_path path)
2133 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
2136 _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC);
2143 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB));
2147 enum rtw89_rf_path path, s8 gain_offset)
2151 txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK);
2160 _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2209 enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
2225 if (_dpk_sync(rtwdev, phy, path, kidx)) {
2240 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD,
2254 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB,
2260 _dpk_bypass_rxcfir(rtwdev, path, true);
2262 _dpk_lbk_rxiqk(rtwdev, phy, path);
2273 _dpk_gainloss(rtwdev, phy, path, kidx);
2291 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3);
2303 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe);
2309 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx);
2356 enum rtw89_rf_path path, u8 kidx, u8 gain)
2360 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
2361 dpk->bp[path][kidx].band == RTW89_BAND_5G)
2366 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL);
2370 enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc)
2376 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2383 dpk->bp[path][kidx].txagc_dpk = txagc;
2384 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
2387 dpk->bp[path][kidx].pwsf = pwsf;
2388 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2391 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2392 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2394 dpk->bp[path][kidx].gs = gs;
2396 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2399 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2402 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2404 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0);
2409 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
2420 if (cur_band != dpk->bp[path][idx].band ||
2421 cur_ch != dpk->bp[path][idx].ch)
2424 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2426 dpk->cur_idx[path] = idx;
2429 "[DPK] reload S%d[%d] success\n", path, idx);
2436 enum rtw89_rf_path path, u8 gain,
2440 u8 txagc = 0x38, kidx = dpk->cur_idx[path];
2444 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
2446 _rfk_rf_direct_cntrl(rtwdev, path, false);
2447 _rfk_drf_direct_cntrl(rtwdev, path, false);
2449 _dpk_kip_pwr_clk_on(rtwdev, path);
2450 _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2451 _dpk_rf_setting(rtwdev, gain, path, kidx);
2452 _dpk_rx_dck(rtwdev, phy, path);
2454 _dpk_kip_preset(rtwdev, phy, path, kidx);
2455 _dpk_kip_set_rxagc(rtwdev, phy, path);
2456 _dpk_table_select(rtwdev, path, kidx, gain);
2458 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx);
2464 _dpk_get_thermal(rtwdev, kidx, path);
2466 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain);
2468 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2470 _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc);
2474 dpk->bp[path][kidx].path_ok = true;
2476 dpk->bp[path][kidx].path_ok = false;
2478 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2494 u8 path;
2497 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
2498 reloaded[path] = _dpk_reload_check(rtwdev, phy, path,
2500 if (!reloaded[path] && dpk->bp[path][0].ch)
2501 dpk->cur_idx[path] = !dpk->cur_idx[path];
2503 _dpk_onoff(rtwdev, path, false);
2506 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++)
2507 dpk->cur_idx[path] = 0;
2512 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
2513 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2514 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2515 _dpk_information(rtwdev, phy, path, chanctx_idx);
2516 if (rtwdev->is_tssi_mode[path])
2517 _dpk_tssi_pause(rtwdev, path, true);
2520 _dpk_bb_afe_setting(rtwdev, phy, path, kpath, chanctx_idx);
2522 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
2523 is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx);
2524 _dpk_onoff(rtwdev, path, is_fail);
2527 _dpk_bb_afe_restore(rtwdev, phy, path, kpath, chanctx_idx);
2530 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
2531 _dpk_kip_restore(rtwdev, path);
2532 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2533 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2534 if (rtwdev->is_tssi_mode[path])
2535 _dpk_tssi_pause(rtwdev, path, false);
2564 u8 path, kpath;
2568 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
2569 if (kpath & BIT(path))
2570 _dpk_onoff(rtwdev, path, true);
2594 u8 path, kidx;
2599 for (path = 0; path < RF_PATH_NUM_8852B; path++) {
2600 kidx = dpk->cur_idx[path];
2604 path, kidx, dpk->bp[path][kidx].ch);
2606 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2611 if (dpk->bp[path][kidx].ch && cur_ther)
2612 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
2614 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2615 delta_ther[path] = delta_ther[path] * 3 / 2;
2617 delta_ther[path] = delta_ther[path] * 5 / 2;
2619 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2622 if (rtwdev->is_tssi_mode[path]) {
2623 trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
2630 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2633 rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13),
2641 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2646 txagc_ofst, delta_ther[path]);
2647 tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
2656 ini_diff = txagc_ofst + (delta_ther[path]);
2659 R_P0_TXDPD + (path << 13),
2662 pwsf[0] = dpk->bp[path][kidx].pwsf +
2664 pwsf[1] = dpk->bp[path][kidx].pwsf +
2667 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff;
2668 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff;
2672 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2673 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2683 R_DPD_BND + (path << 8) + (kidx << 2),
2686 R_DPD_BND + (path << 8) + (kidx << 2),
2695 u8 tx_scale, ofdm_bkof, path, kpath;
2705 for (path = 0; path < RF_PATH_NUM_8852B; path++) {
2706 if (!(kpath & BIT(path)))
2709 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8),
2712 "[RFK] Set S%d DPD backoff to 0dB\n", path);
2720 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2725 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2727 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2731 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2737 if (path == RF_PATH_A)
2749 enum rtw89_rf_path path)
2751 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2758 enum rtw89_rf_path path)
2760 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2766 enum rtw89_rf_path path)
2768 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2774 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2827 if (path == RF_PATH_A) {
2931 enum rtw89_rf_path path)
2933 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2939 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2943 if (path == RF_PATH_A)
2954 enum rtw89_rf_path path, bool all,
2961 if (path == RF_PATH_A) {
3012 enum rtw89_rf_path path)
3014 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3020 enum rtw89_rf_path path)
3022 if (path == RF_PATH_A)
3030 enum rtw89_rf_path path)
3032 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__,
3033 path);
3035 if (path == RF_PATH_A)
3225 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3237 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
3242 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3243 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3247 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3248 path, val, de_1st, de_2nd);
3250 val = tssi_info->tssi_mcs[path][gidx];
3253 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3260 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3272 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3273 path, tgidx);
3278 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3279 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3283 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3284 path, val, tde_1st, tde_2nd);
3286 val = tssi_info->tssi_trim[path][tgidx];
3289 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3290 path, val);
3316 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3333 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3351 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
3356 R_TSSI_PA_K1 + (path << 13),
3357 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
3358 R_TSSI_PA_K2 + (path << 13),
3359 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
3360 R_P0_TSSI_ALIM1 + (path << 13),
3361 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
3362 R_P0_TSSI_ALIM3 + (path << 13),
3363 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
3364 R_TSSI_PA_K5 + (path << 13),
3365 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
3366 R_P0_TSSI_ALIM2 + (path << 13),
3367 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
3368 R_P0_TSSI_ALIM4 + (path << 13),
3369 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
3370 R_TSSI_PA_K8 + (path << 13),
3371 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
3375 enum rtw89_phy_idx phy, enum rtw89_rf_path path,
3383 "======>%s phy=%d path=%d\n", __func__, phy, path);
3396 if (tssi_info->alignment_done[path][band]) {
3397 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3398 tssi_info->alignment_value[path][band][0]);
3399 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3400 tssi_info->alignment_value[path][band][1]);
3401 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3402 tssi_info->alignment_value[path][band][2]);
3403 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3404 tssi_info->alignment_value[path][band][3]);
3407 _tssi_alimentk_dump_result(rtwdev, path);
3411 enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm,
3416 if (path == RF_PATH_A)
3418 else if (path == RF_PATH_B)
3420 else if (path == RF_PATH_AB)
3423 rx_path = RF_ABCD; /* don't change path, but still set others */
3427 rtw8852bx_bb_cfg_tx_path(rtwdev, path);
3485 enum rtw89_rf_path path, const s16 *power,
3494 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0);
3495 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1);
3499 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD);
3501 "[TSSI PA K] 0x%x = 0x%08x path=%d\n",
3502 _tssi_trigger[path], tmp, path);
3505 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true, chan);
3514 "[TSSI PA K] First HWTXcounter=%d path=%d\n",
3515 tx_counter_tmp, path);
3518 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
3530 "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n",
3531 k, tx_counter_tmp, path);
3536 "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n",
3537 k, path);
3539 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3544 rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT);
3546 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3552 "[TSSI PA K] Final HWTXcounter=%d path=%d\n",
3553 tx_counter_tmp, path);
3560 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3583 "======> %s channel=%d path=%d\n", __func__, channel,
3584 path);
3586 if (tssi_info->check_backup_aligmk[path][ch_idx]) {
3587 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3588 tssi_info->alignment_backup_by_ch[path][ch_idx][0]);
3589 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3590 tssi_info->alignment_backup_by_ch[path][ch_idx][1]);
3591 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3592 tssi_info->alignment_backup_by_ch[path][ch_idx][2]);
3593 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3594 tssi_info->alignment_backup_by_ch[path][ch_idx][3]);
3598 _tssi_alimentk_dump_result(rtwdev, path);
3628 ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt, chan);
3638 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1],
3645 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2],
3650 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3],
3655 if (path == RF_PATH_A) {
3685 tssi_info->alignment_done[path][band] = true;
3686 tssi_info->alignment_value[path][band][0] =
3687 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3688 tssi_info->alignment_value[path][band][1] =
3689 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3690 tssi_info->alignment_value[path][band][2] =
3691 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3692 tssi_info->alignment_value[path][band][3] =
3693 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3695 tssi_info->check_backup_aligmk[path][ch_idx] = true;
3696 tssi_info->alignment_backup_by_ch[path][ch_idx][0] =
3697 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3698 tssi_info->alignment_backup_by_ch[path][ch_idx][1] =
3699 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3700 tssi_info->alignment_backup_by_ch[path][ch_idx][2] =
3701 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3702 tssi_info->alignment_backup_by_ch[path][ch_idx][3] =
3703 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3706 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
3707 path, band, R_P0_TSSI_ALIM1 + (path << 13),
3708 tssi_info->alignment_value[path][band][0]);
3710 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
3711 path, band, R_P0_TSSI_ALIM3 + (path << 13),
3712 tssi_info->alignment_value[path][band][1]);
3714 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
3715 path, band, R_P0_TSSI_ALIM2 + (path << 13),
3716 tssi_info->alignment_value[path][band][2]);
3718 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n",
3719 path, band, R_P0_TSSI_ALIM4 + (path << 13),
3720 tssi_info->alignment_value[path][band][3]);
3742 u8 path;
3744 for (path = 0; path < RF_PATH_NUM_8852B; path++)
3745 _rck(rtwdev, path);
3943 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3951 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3954 "[RFK]Invalid RF_0x18 for Path-%d\n", path);
3978 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3980 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
3981 bw, path, reg18_addr,
3982 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
4071 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
4080 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
4093 if (path == RF_PATH_A && dav)
4096 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
4098 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
4099 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
4103 central_ch, path, reg18_addr,
4104 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
4116 enum rtw89_rf_path path)
4118 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
4119 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
4122 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
4124 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
4126 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
4128 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
4130 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
4131 rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
4133 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4139 u8 kpath, path;
4143 for (path = 0; path < RF_PATH_NUM_8852B; path++) {
4144 if (!(kpath & BIT(path)))
4147 _set_rxbb_bw(rtwdev, bw, path);
4195 u8 path;
4200 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++)
4201 _dpk_onoff(rtwdev, path, false);
4205 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++)
4206 _dpk_onoff(rtwdev, path, false);