Lines Matching +full:0 +full:x20040000
21 static const s8 lna_gain_table[] = {15, -1, -17, 0, -30, -38};
22 s8 rx_pwr_all = 0;
30 case 0:
62 /* [31] = 0 --> Page C */
63 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
66 for (i = 0; i < rf_num; i++)
77 /* [31] = 0 --> Page C */
78 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
80 for (i = 0; i < rf_reg_num; i++)
90 /* [31] = 0 --> Page C */
91 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
94 for (i = 0; i < afe_num; i++)
98 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
100 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x0);
101 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x0);
102 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x0);
103 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x3c000000);
104 rtw_write32(rtwdev, REG_LSSI_WRITE_A, 0x00000080);
105 rtw_write32(rtwdev, REG_TXAGCIDX, 0x00000000);
106 rtw_write32(rtwdev, REG_IQK_DPD_CFG, 0x20040000);
107 rtw_write32(rtwdev, REG_CFG_PMPD, 0x20000000);
108 rtw_write32(rtwdev, REG_RFECTL_A, 0x0);
114 /* [31] = 0 --> Page C */
115 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
118 0x000003ff, rx_x >> 1);
120 0x03ff0000, (rx_y >> 1) & 0x3ff);
127 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
129 rtw_write32(rtwdev, REG_LSSI_WRITE_A, 0x00000080);
130 rtw_write32(rtwdev, REG_IQK_DPD_CFG, 0x20040000);
131 rtw_write32(rtwdev, REG_CFG_PMPD, 0x20000000);
132 rtw_write32_mask(rtwdev, REG_IQC_Y, 0x000007ff, tx_y);
133 rtw_write32_mask(rtwdev, REG_IQC_X, 0x000007ff, tx_x);
145 for (k = 0; k < 3; k++) {
147 case 0:
148 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
150 0x18008c38);
151 /* RX_Tone_idx[9:0], RxK_Mask[29] */
152 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c38);
153 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x0);
157 BIT(28), 0x0);
159 BIT(28), 0x0);
160 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x0);
164 "vdf_y[1] = %x vdf_y[0] = %x\n",
165 vdf_y[1] >> 21 & 0x00007ff,
166 vdf_y[0] >> 21 & 0x00007ff);
169 "vdf_x[1] = %x vdf_x[0] = %x\n",
170 vdf_x[1] >> 21 & 0x00007ff,
171 vdf_x[0] >> 21 & 0x00007ff);
173 tx_dt[cal] = (vdf_y[1] >> 20) - (vdf_y[0] >> 20);
175 tx_dt[cal] = (tx_dt[cal] >> 1) + (tx_dt[cal] & BIT(0));
177 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
179 0x18008c20);
180 /* RX_Tone_idx[9:0], RxK_Mask[29] */
181 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c20);
182 rtw_write32_mask(rtwdev, REG_INTPO_SETA, BIT(31), 0x1);
183 rtw_write32_mask(rtwdev, REG_INTPO_SETA, 0x3fff0000,
184 tx_dt[cal] & 0x00003fff);
188 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
190 for (cal_retry = 0; cal_retry < 10; cal_retry++) {
192 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
193 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);
197 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
199 for (delay_count = 0; delay_count < 20; delay_count++) {
228 0x02000000);
231 0x07ff0000);
235 0x04000000);
238 0x07ff0000);
246 0x000007ff, 0x0);
248 0x000007ff, 0x200);
268 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
269 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10);
270 /* RX_Tone_idx[9:0], RxK_Mask[29] */
271 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10);
272 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
274 for (cal_retry = 0; cal_retry < 10; cal_retry++) {
276 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
277 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);
280 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
282 for (delay_count = 0; delay_count < 20; delay_count++) {
306 rtw_write32(rtwdev, REG_RFECTL_A, 0x02000000);
308 0x07ff0000);
311 rtw_write32(rtwdev, REG_RFECTL_A, 0x04000000);
313 0x07ff0000);
320 rtw_write32_mask(rtwdev, REG_IQC_Y, 0x000007ff, 0x0);
321 rtw_write32_mask(rtwdev, REG_IQC_X, 0x000007ff, 0x200);
334 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
336 for (cal_retry = 0; cal_retry < 10; cal_retry++) {
338 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
339 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);
343 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
345 for (delay_count = 0; delay_count < 20; delay_count++) {
363 rtw_write32(rtwdev, REG_RFECTL_A, 0x06000000);
365 0x07ff0000);
368 rtw_write32(rtwdev, REG_RFECTL_A, 0x08000000);
370 0x07ff0000);
378 0x000003ff, 0x200 >> 1);
380 0x03ff0000, 0x0 >> 1);
389 int tx_average = 0, rx_average = 0, rx_iqk_loop = 0;
391 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0;
394 int rx_x_temp = 0, rx_y_temp = 0;
411 for (cal = 0; cal < CAL_NUM_8821A; cal++) {
414 /* [31] = 0 --> Page C */
415 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
418 /* Port 0 DAC/ADC on */
419 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x77777777);
420 rtw_write32(rtwdev, REG_AFE_PWR2_A, 0x77777777);
422 rtw_write32(rtwdev, REG_RX_WAIT_CCA_TX_CCK_RFON_A, 0x19791979);
425 rtw_write32_mask(rtwdev, REG_3WIRE_SWA, 0xf, 0x4);
430 rtw_write32_mask(rtwdev, REG_CK_MONHA, GENMASK(26, 24), 0x7);
433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80002);
434 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x00c00, 0x3);
436 0x20000);
438 0x0003f);
440 0xf3fc3);
443 0x931d5);
444 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x8a001);
445 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000);
446 rtw_write32_mask(rtwdev, REG_TXAGCIDX, BIT(0), 0x1);
448 rtw_write32(rtwdev, REG_IQK_COM00, 0x29002000);
450 rtw_write32(rtwdev, REG_IQK_COM32, 0xa9002000);
451 /* [0]:AGC_en, [15]:idac_K_Mask */
452 rtw_write32(rtwdev, REG_IQK_COM96, 0x00462910);
455 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
459 0x821403f7);
462 0x821403f4);
465 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x68163e96);
467 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28163e96);
469 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
470 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10);
471 /* RX_Tone_idx[9:0], RxK_Mask[29] */
472 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10);
473 rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
474 rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
475 rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);
478 rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
480 /* [31] = 0 --> Page C */
481 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
482 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, 0x7fe00,
483 rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, 0xffc00));
487 RF18_BW_MASK, 0x1);
490 RF18_BW_MASK, 0x0);
493 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
496 /* [31] = 0 --> Page C */
497 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
498 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
500 0x20000);
502 0x0003f);
504 0xf3fc3);
506 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d5);
507 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x8a001);
508 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
509 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000);
510 rtw_write32_mask(rtwdev, REG_TXAGCIDX, BIT(0), 0x1);
512 rtw_write32(rtwdev, REG_IQK_COM00, 0x29002000);
514 rtw_write32(rtwdev, REG_IQK_COM32, 0xa9002000);
515 /* [0]:AGC_en, [15]:idac_K_Mask */
516 rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a910);
519 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
523 0x821403f7);
526 0x821403e3);
529 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x40163e96);
531 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x00163e96);
544 /* [31] = 0 --> Page C */
545 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
547 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
549 0x30000);
551 0x0002f);
553 0xfffbb);
554 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001);
555 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXA_PREPAD, RFREG_MASK, 0x931d8);
556 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
558 rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x03FF8000,
559 (tx_x0[cal] >> 21) & 0x000007ff);
560 rtw_write32_mask(rtwdev, REG_IQK_COM00, 0x000007FF,
561 (tx_y0[cal] >> 21) & 0x000007ff);
562 rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x1);
563 rtw_write32_mask(rtwdev, REG_IQK_COM00, BIT(31), 0x0);
564 rtw_write32(rtwdev, REG_DAC_RSTB, 0x00008000);
565 rtw_write32(rtwdev, REG_IQK_COM96, 0x0046a911);
568 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x1);
570 /* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
571 rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x38008c10);
572 /* RX_Tone_idx[9:0], RxK_Mask[29] */
573 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x18008c10);
574 rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x02140119);
581 for (i = 0; i < rx_iqk_loop; i++) {
582 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && i == 0)
583 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28161100); /* Good */
585 rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28160d00);
599 if (tx_average == 0)
602 for (i = 0; i < tx_average; i++)
605 i, (tx_x0[i] >> 21) & 0x000007ff,
606 i, (tx_y0[i] >> 21) & 0x000007ff);
612 rtw8821a_iqk_tx_fill(rtwdev, 0x200, 0x0);
614 if (rx_average == 0)
617 for (i = 0; i < rx_average; i++) {
619 "rx_x0[0][%d] = %x ;; rx_y0[0][%d] = %x\n",
620 i, (rx_x0[0][i] >> 21) & 0x000007ff,
621 i, (rx_y0[0][i] >> 21) & 0x000007ff);
626 i, (rx_x0[1][i] >> 21) & 0x000007ff,
627 i, (rx_y0[1][i] >> 21) & 0x000007ff);
630 rx_finish1 = rtw88xxa_iqk_finish(rx_average, 4, rx_x0[0], rx_y0[0],
652 rtw8821a_iqk_rx_fill(rtwdev, 0x200, 0x0);
658 0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c
661 0xc5c, 0xc60, 0xc64, 0xc68
664 0x65, 0x8f, 0x0
700 GENMASK(17, 16), 0x03);
746 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
754 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x3);
780 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1);
788 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1);
797 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000, 0x1);
805 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000,
806 share_ant ? 0x2 : 0x1);
814 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, 0x30000000,
815 share_ant ? 0x2 : 0x1);
896 {0, 0, 0, 0, 0}, /* SDIO */
897 {0, 0, 0, 0, 0}, /* PCI */
898 {8, 0, 0, 0, 1}, /* 2 bulk out endpoints */
899 {8, 0, 8, 0, 1}, /* 3 bulk out endpoints */
900 {8, 0, 8, 4, 1}, /* 4 bulk out endpoints */
942 [0] = { .addr = REG_RXIGI_A, .mask = 0x7f },
946 [0] = { .phy_pg_tbl = &rtw8821a_bb_pg_tbl,
960 * tdma case 112 (A2DP) byte 0 had to be modified from 0x61 to 0x51,
962 * rtw_8821au 1-2:1.2: [BTCoex], Bt_info[1], len=7, data=[81 00 0a 01 00 00]
969 {0x55555555, 0x55555555}, /* case-0 */
970 {0x55555555, 0x55555555},
971 {0x66555555, 0x66555555},
972 {0xaaaaaaaa, 0xaaaaaaaa},
973 {0x5a5a5a5a, 0x5a5a5a5a},
974 {0xfafafafa, 0xfafafafa}, /* case-5 */
975 {0x6a5a5555, 0xaaaaaaaa},
976 {0x6a5a56aa, 0x6a5a56aa},
977 {0x6a5a5a5a, 0x6a5a5a5a},
978 {0x66555555, 0x5a5a5a5a},
979 {0x66555555, 0x6a5a5a5a}, /* case-10 */
980 {0x66555555, 0xaaaaaaaa},
981 {0x66555555, 0x6a5a5aaa},
982 {0x66555555, 0x6aaa6aaa},
983 {0x66555555, 0x6a5a5aaa},
984 {0x66555555, 0xaaaaaaaa}, /* case-15 */
985 {0xffff55ff, 0xfafafafa},
986 {0xffff55ff, 0x6afa5afa},
987 {0xaaffffaa, 0xfafafafa},
988 {0xaa5555aa, 0x5a5a5a5a},
989 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
990 {0xaa5555aa, 0xaaaaaaaa},
991 {0xffffffff, 0x55555555},
992 {0xffffffff, 0x5a5a5a5a},
993 {0xffffffff, 0x5a5a5a5a},
994 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
995 {0x55555555, 0x5a5a5a5a},
996 {0x55555555, 0xaaaaaaaa},
997 {0x66555555, 0x6a5a6a5a},
998 {0x66556655, 0x66556655},
999 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1000 {0xffffffff, 0x5aaa5aaa},
1001 {0x56555555, 0x5a5a5aaa}
1006 {0xffffffff, 0xffffffff}, /* case-100 */
1007 {0xffff55ff, 0xfafafafa},
1008 {0x66555555, 0x66555555},
1009 {0xaaaaaaaa, 0xaaaaaaaa},
1010 {0x5a5a5a5a, 0x5a5a5a5a},
1011 {0xffffffff, 0xffffffff}, /* case-105 */
1012 {0x5afa5afa, 0x5afa5afa},
1013 {0x55555555, 0xfafafafa},
1014 {0x66555555, 0xfafafafa},
1015 {0x66555555, 0x5a5a5a5a},
1016 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1017 {0x66555555, 0xaaaaaaaa},
1018 {0xffff55ff, 0xfafafafa},
1019 {0xffff55ff, 0x5afa5afa},
1020 {0xffff55ff, 0xaaaaaaaa},
1021 {0xffff55ff, 0xffff55ff}, /* case-115 */
1022 {0xaaffffaa, 0x5afa5afa},
1023 {0xaaffffaa, 0xaaaaaaaa},
1024 {0xffffffff, 0xfafafafa},
1025 {0xffff55ff, 0xfafafafa},
1026 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1027 {0xffff55ff, 0x5afa5afa},
1028 {0xffff55ff, 0x5afa5afa},
1029 {0x55ff55ff, 0x55ff55ff}
1034 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1035 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1036 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1037 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1038 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1039 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1040 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1041 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1042 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1043 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1044 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1045 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1046 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1047 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1048 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1049 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1050 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1051 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1052 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1053 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1054 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1055 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1056 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1057 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1058 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1059 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1060 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1061 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1066 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1067 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1068 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1069 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1070 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1071 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1072 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1073 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1074 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1075 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1076 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1077 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1078 { {0x51, 0x08, 0x03, 0x10, 0x14} }, /* a2dp high rssi */
1079 { {0x51, 0x08, 0x03, 0x10, 0x54} }, /* a2dp not high rssi */
1080 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1081 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1082 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1083 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1084 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1085 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1086 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1087 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1092 {0, 0, false, 7}, /* for normal */
1093 {0, 20, false, 7}, /* for WL-CPT */
1101 {0, 0, false, 7}, /* for normal */
1102 {0, 20, false, 7}, /* for WL-CPT */
1106 {0, 28, true, 5}
1111 static const struct coex_5g_afh_map afh_5g_8821a[] = { {0, 0, 0} };
1114 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1115 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1116 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1117 {0, 0, RTW_REG_DOMAIN_NL},
1118 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1119 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1120 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1121 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1122 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1123 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1124 {0, 0, RTW_REG_DOMAIN_NL},
1125 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1126 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1127 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1128 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1129 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1130 {0, 0, RTW_REG_DOMAIN_NL},
1131 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1132 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1133 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1134 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1135 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1149 .ptct_efuse_size = 0,
1155 .max_power_index = 0x3f,
1156 .csi_buf_pg_num = 0,
1159 .dig_min = 0x20,
1162 .lps_deep_mode_supported = 0,
1163 .sys_func_en = 0xFD,
1190 .bt_desired_ver = 0x62, /* But for 2 ant it's 0x5c */
1212 .bt_afh_span_bw20 = 0x20,
1213 .bt_afh_span_bw40 = 0x30,