Lines Matching defs:bw
1614 u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1625 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1628 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1629 regd, band, bw, rs, ch_idx, pwr_limit);
1634 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1635 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1637 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1639 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1640 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1642 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1649 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1653 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1654 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1660 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1663 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1668 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1682 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1688 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1693 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1700 u8 bw;
1702 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1703 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1716 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1721 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1722 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1725 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1726 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1732 u8 bw, rs;
1734 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1737 bw, rs);
1752 p->bw, p->rs, p->ch, p->txpwr_lmt);
2150 enum rtw_bandwidth bw, u8 rf_path,
2169 bw = RTW_CHANNEL_WIDTH_20;
2173 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
2176 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
2193 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
2194 band, bw, rf_path, rate, channel);
2219 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
2240 bw, rate, group);
2246 bw, rate, group);
2250 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
2294 u8 bw;
2302 bw = hal->current_band_width;
2306 bw, ch, regd);
2382 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2389 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2394 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2400 u8 regd, bw, rs;
2406 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2408 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2412 u8 regd, u8 bw, u8 rs)
2420 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2424 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2430 u8 regd, path, rate, rs, bw;
2442 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2444 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,