Lines Matching refs:rtl_set_bbreg
53 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3);
56 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
64 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
66 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
70 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
73 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
75 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
84 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
87 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
209 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
217 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
246 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
268 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
308 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000,
312 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
333 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770);
334 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770);
335 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
336 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
337 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
340 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
341 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
342 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001);
343 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001);
347 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
350 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
354 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777);
355 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
357 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
358 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
365 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
366 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
367 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
368 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
381 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717);
382 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717);
383 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
384 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
388 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717);
389 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
391 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
392 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
394 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
396 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
398 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
399 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
403 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717);
404 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717);
405 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
406 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
407 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
411 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
414 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
419 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
420 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
421 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
422 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
599 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
603 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
605 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
610 rtl_set_bbreg(hw, 0x834, 0x3, 0x1);
615 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0);
618 rtl_set_bbreg(hw, 0x82c, 0x3, 0);
624 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1);
625 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1);
633 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
635 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
662 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
666 rtl_set_bbreg(hw, 0x834, 0x3, 0x2);
672 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1);
675 rtl_set_bbreg(hw, 0x82c, 0x3, 1);
680 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0);
681 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf);
691 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
694 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
878 rtl_set_bbreg(hw, addr, MASKDWORD, data);
2722 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2726 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2730 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2734 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2738 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2742 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2746 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2750 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2754 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2758 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2762 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2766 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2770 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2774 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2778 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2782 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2786 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2790 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2794 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2798 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2802 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2806 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2810 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2814 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2818 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2822 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2826 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2830 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2834 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2838 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2842 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2846 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2850 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2854 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2858 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2862 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2866 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2870 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2874 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2878 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2882 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2886 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2890 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2894 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2898 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2902 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2906 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2910 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2921 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2925 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2929 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2933 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2937 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2941 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2945 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2949 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2953 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2957 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2961 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2965 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2969 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2973 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2977 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2981 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2985 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
2989 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
2993 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
2997 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3001 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3005 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3009 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3013 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3017 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3021 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3025 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3029 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3033 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3037 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3041 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3045 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3049 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3053 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3057 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3061 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3065 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3069 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3073 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3077 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3081 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3085 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3089 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3093 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3097 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3101 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3105 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3109 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3177 rtl_set_bbreg(hw, offset, 0xffffff, data);
3390 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
3391 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3394 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
3396 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
3399 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
3400 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3401 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3402 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3413 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3416 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
3418 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
3423 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202);
3425 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
3426 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3427 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3437 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3499 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3604 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3618 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3632 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3649 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3651 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3653 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/
3663 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1);
3667 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3668 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3688 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3689 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
3690 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
3732 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3746 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3751 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3761 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3764 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3769 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3786 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3800 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3803 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3814 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3819 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3833 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3836 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
3837 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
3838 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3850 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
3851 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
3888 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3889 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3942 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3943 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3962 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */
3966 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3976 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3982 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3988 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
3995 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4015 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4079 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4089 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4090 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4091 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4092 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4093 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4097 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4098 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4099 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4105 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */
4138 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4139 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4159 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */
4164 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4177 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4236 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4246 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4247 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4248 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4249 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4254 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4293 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4294 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4314 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4406 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4428 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4432 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4453 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4508 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
4510 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);