Lines Matching refs:rtl_set_bbreg
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
272 rtl_set_bbreg(hw, addr, MASKDWORD, data);
1229 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1230 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1231 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1234 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1235 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1237 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1239 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1240 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1242 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1457 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1459 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1469 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1470 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1472 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1473 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1474 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1475 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1477 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1478 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1479 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1480 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1482 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1484 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1487 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1488 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1493 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1530 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1533 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1542 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1545 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1546 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1549 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1550 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1551 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1552 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1554 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1555 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1556 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1557 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1560 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1563 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1566 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1567 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1572 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1601 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1605 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1617 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1620 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1621 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1622 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1623 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1625 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1626 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1627 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1628 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1631 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1634 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1637 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1638 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1650 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1677 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1679 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1687 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1688 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1690 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1691 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1692 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1693 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1695 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1696 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1697 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1698 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1701 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1704 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1707 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1708 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1713 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1750 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1752 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1766 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1767 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1770 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1771 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1772 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1773 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1775 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1776 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1777 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1778 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1781 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1783 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1786 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1787 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1792 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1820 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1825 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1837 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1840 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1841 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1842 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1843 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1845 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1846 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1847 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1848 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1851 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1853 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1856 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1857 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1862 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1906 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1907 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1913 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1915 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1917 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1922 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1924 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1926 /* rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); */
2058 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf);
2059 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
2060 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
2061 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2147 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
2150 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2151 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50);
2153 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, 0x50);
2154 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_reg_c58);
2156 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
2157 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
2244 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);
2246 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);
2386 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
2474 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2479 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);