Lines Matching defs:rt2x00dev
66 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69 if (!rt2x00_is_soc(rt2x00dev) ||
70 !rt2x00_rt(rt2x00dev, RT2872))
74 if (rt2x00_rf(rt2x00dev, RF3020) ||
75 rt2x00_rf(rt2x00dev, RF3021) ||
76 rt2x00_rf(rt2x00dev, RF3022))
79 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
83 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 mutex_lock(&rt2x00dev->csr_mutex);
94 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
102 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 mutex_unlock(&rt2x00dev->csr_mutex);
108 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
113 mutex_lock(&rt2x00dev->csr_mutex);
123 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
130 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
132 WAIT_FOR_BBP(rt2x00dev, ®);
137 mutex_unlock(&rt2x00dev->csr_mutex);
142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
147 mutex_lock(&rt2x00dev->csr_mutex);
153 switch (rt2x00dev->chip.rt) {
155 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
163 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
168 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
175 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
180 mutex_unlock(&rt2x00dev->csr_mutex);
183 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
186 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
189 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
192 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
193 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
196 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
199 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
200 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
203 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
206 rt2800_bbp_write(rt2x00dev, 158, reg);
207 rt2800_bbp_write(rt2x00dev, 159, value);
210 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
212 rt2800_bbp_write(rt2x00dev, 158, reg);
213 return rt2800_bbp_read(rt2x00dev, 159);
216 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
219 rt2800_bbp_write(rt2x00dev, 195, reg);
220 rt2800_bbp_write(rt2x00dev, 196, value);
223 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
229 mutex_lock(&rt2x00dev->csr_mutex);
239 switch (rt2x00dev->chip.rt) {
241 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
250 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®);
257 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
263 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
265 WAIT_FOR_RFCSR(rt2x00dev, ®);
272 mutex_unlock(&rt2x00dev->csr_mutex);
277 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
280 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
283 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
288 mutex_lock(&rt2x00dev->csr_mutex);
294 if (WAIT_FOR_RF(rt2x00dev, ®)) {
301 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
302 rt2x00_rf_write(rt2x00dev, word, value);
305 mutex_unlock(&rt2x00dev->csr_mutex);
388 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
396 wiphy_name(rt2x00dev->hw->wiphy), word))
399 if (rt2x00_rt(rt2x00dev, RT3593) ||
400 rt2x00_rt(rt2x00dev, RT3883))
415 wiphy_name(rt2x00dev->hw->wiphy), word);
420 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
425 index = rt2800_eeprom_word_index(rt2x00dev, word);
426 return rt2x00_eeprom_addr(rt2x00dev, index);
429 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
434 index = rt2800_eeprom_word_index(rt2x00dev, word);
435 return rt2x00_eeprom_read(rt2x00dev, index);
438 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
443 index = rt2800_eeprom_word_index(rt2x00dev, word);
444 rt2x00_eeprom_write(rt2x00dev, index, data);
447 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
453 index = rt2800_eeprom_word_index(rt2x00dev, array);
454 return rt2x00_eeprom_read(rt2x00dev, index + offset);
457 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
462 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
467 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
477 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
489 rt2800_register_write(rt2x00dev, 0x58, 0x018);
491 rt2800_register_write(rt2x00dev, 0x58, 0x418);
493 rt2800_register_write(rt2x00dev, 0x58, 0x618);
500 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
504 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
507 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
509 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
515 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
524 if (rt2x00_is_soc(rt2x00dev))
527 mutex_lock(&rt2x00dev->csr_mutex);
533 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
538 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
542 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
545 mutex_unlock(&rt2x00dev->csr_mutex);
549 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
555 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
561 rt2x00_err(rt2x00dev, "Unstable hardware\n");
566 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
576 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
584 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
589 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
593 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
599 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
603 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
607 switch (rt2x00dev->chip.rt) {
660 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
676 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
692 if (rt2x00_is_usb(rt2x00dev) &&
693 !rt2x00_rt(rt2x00dev, RT2860) &&
694 !rt2x00_rt(rt2x00dev, RT2872) &&
695 !rt2x00_rt(rt2x00dev, RT3070) &&
714 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
721 if (rt2x00_rt(rt2x00dev, RT3290)) {
722 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
731 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
736 if (rt2800_wait_csr_ready(rt2x00dev))
739 if (rt2x00_is_pci(rt2x00dev)) {
740 if (rt2x00_rt(rt2x00dev, RT3290) ||
741 rt2x00_rt(rt2x00dev, RT3572) ||
742 rt2x00_rt(rt2x00dev, RT5390) ||
743 rt2x00_rt(rt2x00dev, RT5392)) {
744 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
747 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
749 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
752 rt2800_disable_wpdma(rt2x00dev);
757 rt2800_drv_write_firmware(rt2x00dev, data, len);
763 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
770 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
778 rt2800_disable_wpdma(rt2x00dev);
783 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
784 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
785 if (rt2x00_is_usb(rt2x00dev)) {
786 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
787 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
856 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
861 s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12;
867 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
868 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
871 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
874 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
877 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
886 rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
887 rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
888 rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
937 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
1010 rt2x00_dbg(entry->queue->rt2x00dev,
1022 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1023 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1065 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1096 txdesc.retry = rt2x00dev->long_retry;
1121 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1129 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {
1135 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1138 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1147 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1158 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1167 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1174 rt2x00_dbg(entry->queue->rt2x00dev,
1180 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1185 tx_queue_for_each(rt2x00dev, queue) {
1187 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1199 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1203 tx_queue_for_each(rt2x00dev, queue) {
1212 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1224 tx_queue_for_each(rt2x00dev, queue) {
1233 rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1255 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
1257 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1259 &rt2x00dev->chan_survey[chan->hw_value];
1261 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1262 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1263 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1266 static bool rt2800_watchdog_hung(struct rt2x00_dev *rt2x00dev)
1272 rt2800_update_survey(rt2x00dev);
1274 queue_for_each(rt2x00dev, queue) {
1290 if (rt2x00dev->intf_sta_count == 0)
1303 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1306 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1308 queue_for_each(rt2x00dev, queue)
1314 static bool rt2800_watchdog_dma_busy(struct rt2x00_dev *rt2x00dev)
1317 u32 reg_cfg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
1318 u32 reg_int = rt2800_register_read(rt2x00dev, INT_SOURCE_CSR);
1322 rt2x00dev->rxdma_busy++;
1324 rt2x00dev->rxdma_busy = 0;
1328 rt2x00dev->txdma_busy++;
1330 rt2x00dev->txdma_busy = 0;
1332 busy_rx = rt2x00dev->rxdma_busy > 30;
1333 busy_tx = rt2x00dev->txdma_busy > 30;
1339 rt2x00_warn(rt2x00dev, "Watchdog RX DMA busy detected\n");
1342 rt2x00_warn(rt2x00dev, "Watchdog TX DMA busy detected\n");
1344 rt2x00dev->rxdma_busy = 0;
1345 rt2x00dev->txdma_busy = 0;
1350 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1354 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1357 if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_DMA_BUSY)
1358 reset = rt2800_watchdog_dma_busy(rt2x00dev);
1360 if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_HANG)
1361 reset = rt2800_watchdog_hung(rt2x00dev) || reset;
1364 ieee80211_restart_hw(rt2x00dev->hw);
1368 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1374 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1377 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1380 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1382 struct data_queue *queue = rt2x00dev->bcn;
1395 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1400 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1401 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1406 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1409 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1414 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1425 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1428 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1450 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1457 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1460 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1464 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1466 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1473 rt2800_update_beacons_setup(rt2x00dev);
1478 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1488 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1492 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1495 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1503 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1508 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1515 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1518 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1523 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1529 rt2800_update_beacons_setup(rt2x00dev);
1533 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1583 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1587 if (rt2x00_rt(rt2x00dev, RT3290)) {
1588 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1591 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1605 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1607 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1610 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1615 if (rt2x00_is_soc(led->rt2x00dev)) {
1616 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1633 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1637 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1640 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1651 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1658 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1661 led->rt2x00dev = rt2x00dev;
1671 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1684 rt2800_register_multiwrite(rt2x00dev, offset,
1688 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1692 rt2800_register_write(rt2x00dev, offset, 0);
1695 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1705 reg = rt2800_register_read(rt2x00dev, offset);
1709 rt2800_register_write(rt2x00dev, offset, reg);
1712 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1723 reg = rt2800_register_read(rt2x00dev, offset);
1736 rt2800_register_write(rt2x00dev, offset, reg);
1739 reg = rt2800_register_read(rt2x00dev, offset);
1744 rt2800_register_write(rt2x00dev, offset, reg);
1747 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1758 rt2800_register_multiwrite(rt2x00dev, offset,
1762 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1782 rt2800_register_multiwrite(rt2x00dev, offset,
1798 reg = rt2800_register_read(rt2x00dev, offset);
1801 rt2800_register_write(rt2x00dev, offset, reg);
1806 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1807 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1809 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1815 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1839 rt2800_register_multiwrite(rt2x00dev, offset,
1846 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1852 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1856 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1864 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1866 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1872 struct rt2x00_dev *rt2x00dev = hw->priv;
1873 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1885 rt2800_set_max_psdu_len(rt2x00dev);
1913 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1914 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1915 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1916 rt2x00lib_get_bssidx(rt2x00dev, vif));
1924 struct rt2x00_dev *rt2x00dev = hw->priv;
1925 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1931 rt2800_set_max_psdu_len(rt2x00dev);
1940 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1948 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1950 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1951 struct data_queue *queue = rt2x00dev->bcn;
1967 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1978 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1984 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
2008 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
2012 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
2022 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2024 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2030 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
2035 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
2037 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
2042 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
2063 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
2075 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
2081 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2156 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2159 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2161 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2164 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2166 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2169 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2171 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2174 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2177 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2183 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2186 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2190 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2193 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2197 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2199 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2203 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2206 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2208 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2210 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2214 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2217 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2221 rt2800_config_ht_opmode(rt2x00dev, erp);
2225 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,
2232 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
2239 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
2243 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2252 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2253 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2257 value = rt2800_bbp_read(rt2x00dev, 0);
2263 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
2267 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2273 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2274 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2281 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2283 reg = rt2800_register_read(rt2x00dev, LED_CFG);
2288 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2293 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2295 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2301 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2308 if (rt2x00_is_pci(rt2x00dev)) {
2309 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2311 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2312 } else if (rt2x00_is_usb(rt2x00dev))
2313 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2316 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2319 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2322 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2328 r1 = rt2800_bbp_read(rt2x00dev, 1);
2329 r3 = rt2800_bbp_read(rt2x00dev, 3);
2331 if (rt2x00_rt(rt2x00dev, RT3572) &&
2332 rt2x00_has_cap_bt_coexist(rt2x00dev))
2333 rt2800_config_3572bt_ant(rt2x00dev);
2343 if (rt2x00_rt(rt2x00dev, RT3572) &&
2344 rt2x00_has_cap_bt_coexist(rt2x00dev))
2359 if (rt2x00_rt(rt2x00dev, RT3070) ||
2360 rt2x00_rt(rt2x00dev, RT3090) ||
2361 rt2x00_rt(rt2x00dev, RT3352) ||
2362 rt2x00_rt(rt2x00dev, RT3390)) {
2363 eeprom = rt2800_eeprom_read(rt2x00dev,
2367 rt2800_set_ant_diversity(rt2x00dev,
2368 rt2x00dev->default_ant.rx);
2373 if (rt2x00_rt(rt2x00dev, RT3572) &&
2374 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2377 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2378 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2388 rt2800_bbp_write(rt2x00dev, 3, r3);
2389 rt2800_bbp_write(rt2x00dev, 1, r1);
2391 if (rt2x00_rt(rt2x00dev, RT3593) ||
2392 rt2x00_rt(rt2x00dev, RT3883)) {
2394 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2396 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2401 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2408 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2411 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2414 if (rt2x00_rt(rt2x00dev, RT3593) ||
2415 rt2x00_rt(rt2x00dev, RT3883)) {
2416 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2420 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2425 if (rt2x00_rt(rt2x00dev, RT3593) ||
2426 rt2x00_rt(rt2x00dev, RT3883)) {
2427 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2431 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2437 rt2x00dev->lna_gain = lna_gain;
2440 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2442 return clk_get_rate(rt2x00dev->clk) == 20000000;
2447 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2452 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2455 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2462 if (rt2x00_is_usb(rt2x00dev)) {
2463 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2476 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2482 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2487 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2489 if (rt2x00dev->default_ant.tx_chain_num == 1)
2492 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2495 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2527 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2528 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2529 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2530 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2534 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2535 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2536 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2537 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2541 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2542 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2543 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2544 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2547 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2552 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2555 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2557 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2559 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2561 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2563 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2565 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2567 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2569 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2571 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2573 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2576 rt2x00dev->default_ant.rx_chain_num <= 1);
2578 rt2x00dev->default_ant.rx_chain_num <= 2);
2581 rt2x00dev->default_ant.tx_chain_num <= 1);
2583 rt2x00dev->default_ant.tx_chain_num <= 2);
2584 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2586 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2587 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2588 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2590 if (rt2x00_rt(rt2x00dev, RT3390)) {
2603 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2605 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2607 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2609 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2611 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2613 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2615 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2617 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2622 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2625 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2630 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2635 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2636 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2638 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2639 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2642 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2643 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2645 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2651 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2653 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2658 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2660 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2671 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2673 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2684 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2686 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2693 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2701 switch (rt2x00dev->default_ant.tx_chain_num) {
2710 switch (rt2x00dev->default_ant.rx_chain_num) {
2719 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2721 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2722 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2723 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2726 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2727 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2729 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2730 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2734 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2735 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2736 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2737 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2738 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2742 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2743 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2744 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2745 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2746 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2747 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2748 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2749 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2751 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2756 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2757 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2758 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2759 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2760 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2764 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2765 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2767 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2768 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2769 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2771 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2772 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2773 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2775 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2776 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2777 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2779 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2780 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2781 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2784 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2790 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2792 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2794 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2797 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2802 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2810 bbp = rt2800_bbp_read(rt2x00dev, 109);
2813 rt2800_bbp_write(rt2x00dev, 109, bbp);
2815 bbp = rt2800_bbp_read(rt2x00dev, 110);
2817 rt2800_bbp_write(rt2x00dev, 110, bbp);
2821 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2822 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2827 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2829 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2832 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2833 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2835 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2837 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2845 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2847 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2853 if (rt2x00_is_usb(rt2x00dev))
2860 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2862 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2868 if (rt2x00_is_usb(rt2x00dev))
2875 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2877 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2883 if (rt2x00_is_usb(rt2x00dev))
2890 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2892 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2902 switch (rt2x00dev->default_ant.tx_chain_num) {
2914 switch (rt2x00dev->default_ant.rx_chain_num) {
2925 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2927 rt2800_freq_cal_mode1(rt2x00dev);
2944 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2951 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2953 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2956 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2959 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2964 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2966 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2971 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2973 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2978 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2980 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2989 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2991 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2993 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2995 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2998 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2999 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3001 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
3002 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
3005 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3007 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3009 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3017 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3019 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3028 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3030 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3032 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3034 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3039 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
3042 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3043 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3045 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3046 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3050 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3061 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3067 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3069 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
3074 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
3076 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
3081 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3083 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
3088 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3090 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
3094 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
3108 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3110 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
3112 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3114 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3115 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3118 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
3120 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
3123 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
3125 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3127 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3129 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3139 switch (rt2x00dev->default_ant.tx_chain_num) {
3151 switch (rt2x00dev->default_ant.rx_chain_num) {
3162 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3164 rt2800_freq_cal_mode1(rt2x00dev);
3166 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3171 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3174 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3176 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3179 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3181 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3184 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3186 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3189 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3194 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3208 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3211 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3213 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3223 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3233 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3235 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3237 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3239 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3241 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3243 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3245 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3247 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3262 rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3263 rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3264 rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3266 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3271 rt2800_bbp_write(rt2x00dev, 109, bbp);
3273 bbp = rt2800_bbp_read(rt2x00dev, 110);
3276 rt2800_bbp_write(rt2x00dev, 110, bbp);
3278 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3280 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3282 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3285 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3287 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3291 bbp = rt2800_bbp_read(rt2x00dev, 49);
3293 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3294 rt2800_bbp_write(rt2x00dev, 49, bbp);
3302 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3309 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3310 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3311 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3313 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3315 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3320 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3322 rt2800_freq_cal_mode1(rt2x00dev);
3326 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3328 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3331 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3333 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3335 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3339 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3346 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3347 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3349 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3350 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3351 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3354 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3356 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3359 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3361 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3363 rt2800_freq_cal_mode1(rt2x00dev);
3365 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3369 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3374 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3382 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3384 rt2800_rfcsr_write(rt2x00dev, 31, 80);
3387 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3395 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3396 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3397 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3399 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3401 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3406 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3408 if (rt2x00_rt(rt2x00dev, RT5392)) {
3409 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3415 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3418 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3419 if (rt2x00_rt(rt2x00dev, RT5392)) {
3427 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3429 rt2800_freq_cal_mode1(rt2x00dev);
3431 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3432 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3441 rt2800_rfcsr_write(rt2x00dev, 55,
3443 rt2800_rfcsr_write(rt2x00dev, 59,
3450 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3453 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3461 rt2800_rfcsr_write(rt2x00dev, 55,
3463 rt2800_rfcsr_write(rt2x00dev, 59,
3465 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3466 rt2x00_rt(rt2x00dev, RT5392) ||
3467 rt2x00_rt(rt2x00dev, RT6352)) {
3472 rt2800_rfcsr_write(rt2x00dev, 59,
3474 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3479 rt2800_rfcsr_write(rt2x00dev, 59,
3485 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3498 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3501 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3504 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3506 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3510 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3512 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3515 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3518 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3520 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3521 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3522 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3523 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3524 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3525 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3526 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3527 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3528 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3529 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3530 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3531 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3532 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3533 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3534 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3535 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3536 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3537 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3538 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3539 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3540 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3541 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3542 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3543 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3544 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3545 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3546 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3547 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3552 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3553 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3557 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3558 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3560 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3562 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3566 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3568 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3574 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3576 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3577 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3578 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3579 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3580 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3581 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3582 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3583 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3584 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3585 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3586 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3587 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3588 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3589 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3595 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3596 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3597 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3598 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3600 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3602 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3603 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3604 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3605 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3606 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3607 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3608 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3609 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3611 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3612 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3614 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3615 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3618 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3619 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3620 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3624 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3625 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3626 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3628 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3629 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3631 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3632 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3635 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3636 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3637 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3638 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3640 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3641 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3642 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3643 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3646 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3648 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3650 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3652 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3653 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3655 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3657 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3659 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3661 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3663 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3665 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3667 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3669 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3671 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3673 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3680 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3687 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3689 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3696 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3698 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3703 rt2x00dev->default_ant.tx_chain_num >= 1);
3705 rt2x00dev->default_ant.tx_chain_num == 2);
3709 rt2x00dev->default_ant.rx_chain_num >= 1);
3711 rt2x00dev->default_ant.rx_chain_num == 2);
3714 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3715 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3718 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3720 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3723 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3724 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3728 rt2800_freq_cal_mode1(rt2x00dev);
3731 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3733 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3736 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3737 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3738 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3740 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3741 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3742 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3743 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3746 rt2800_bbp_write(rt2x00dev, 195, 128);
3747 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3748 rt2800_bbp_write(rt2x00dev, 195, 129);
3749 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3750 rt2800_bbp_write(rt2x00dev, 195, 130);
3751 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3752 rt2800_bbp_write(rt2x00dev, 195, 131);
3753 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3754 rt2800_bbp_write(rt2x00dev, 195, 133);
3755 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3756 rt2800_bbp_write(rt2x00dev, 195, 124);
3757 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3760 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3765 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3773 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3775 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3776 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3782 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3784 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3786 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3788 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3793 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3795 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3800 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3802 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3809 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3811 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3813 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3815 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3817 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3819 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3822 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3824 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3826 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3828 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3830 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3832 rt2x00dev->default_ant.tx_chain_num != 1);
3833 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3835 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3837 rt2x00dev->default_ant.tx_chain_num != 1);
3839 rt2x00dev->default_ant.rx_chain_num != 1);
3840 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3842 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3844 rt2x00dev->default_ant.tx_chain_num != 1);
3845 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3849 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3850 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3851 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3852 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3853 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3855 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3856 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3857 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3858 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3859 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3863 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3864 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3866 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3867 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3870 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3873 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3875 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3883 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3886 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3887 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3890 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3891 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3894 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3895 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3898 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3900 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3903 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3904 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3907 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3908 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3911 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3912 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3915 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3919 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
3923 int cur_channel = rt2x00dev->rf_channel;
3943 rate_power = rt2800_eeprom_read_from_array(rt2x00dev,
3950 power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3951 power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3959 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3965 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3968 target_power = rt2800_eeprom_read(rt2x00dev,
3973 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3975 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3977 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3980 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3982 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3984 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
3985 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
3988 bbp = rt2800_bbp_read(rt2x00dev, 30);
3990 rt2800_bbp_write(rt2x00dev, 30, bbp);
3991 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3992 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3993 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3995 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3997 bbp = rt2800_bbp_read(rt2x00dev, 30);
3999 rt2800_bbp_write(rt2x00dev, 30, bbp);
4000 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
4001 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
4002 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
4004 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4006 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
4008 rt2800_vco_calibration(rt2x00dev);
4011 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
4017 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
4018 reg = rt2800_bbp_read(rt2x00dev, 27);
4020 rt2800_bbp_write(rt2x00dev, 27, reg);
4022 rt2800_bbp_write(rt2x00dev, word, value);
4026 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
4031 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
4033 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
4035 cal = rt2x00_eeprom_byte(rt2x00dev,
4038 cal = rt2x00_eeprom_byte(rt2x00dev,
4041 cal = rt2x00_eeprom_byte(rt2x00dev,
4045 rt2800_bbp_write(rt2x00dev, 159, cal);
4048 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
4050 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
4052 cal = rt2x00_eeprom_byte(rt2x00dev,
4055 cal = rt2x00_eeprom_byte(rt2x00dev,
4058 cal = rt2x00_eeprom_byte(rt2x00dev,
4062 rt2800_bbp_write(rt2x00dev, 159, cal);
4065 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
4067 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
4069 cal = rt2x00_eeprom_byte(rt2x00dev,
4072 cal = rt2x00_eeprom_byte(rt2x00dev,
4075 cal = rt2x00_eeprom_byte(rt2x00dev,
4079 rt2800_bbp_write(rt2x00dev, 159, cal);
4082 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
4084 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
4086 cal = rt2x00_eeprom_byte(rt2x00dev,
4089 cal = rt2x00_eeprom_byte(rt2x00dev,
4092 cal = rt2x00_eeprom_byte(rt2x00dev,
4096 rt2800_bbp_write(rt2x00dev, 159, cal);
4101 rt2800_bbp_write(rt2x00dev, 158, 0x04);
4102 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
4103 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4106 rt2800_bbp_write(rt2x00dev, 158, 0x03);
4107 cal = rt2x00_eeprom_byte(rt2x00dev,
4109 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4112 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4116 if (rt2x00_rt(rt2x00dev, RT3593) ||
4117 rt2x00_rt(rt2x00dev, RT3883))
4123 if (rt2x00_rt(rt2x00dev, RT3593) ||
4124 rt2x00_rt(rt2x00dev, RT3883))
4131 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
4137 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4139 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4142 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4145 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4148 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4151 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4152 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4153 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4155 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4156 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4157 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4161 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4170 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4172 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4174 if (rt2x00dev->default_ant.tx_chain_num > 2)
4176 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4179 switch (rt2x00dev->chip.rt) {
4181 rt3883_bbp_adjust(rt2x00dev, rf);
4185 switch (rt2x00dev->chip.rf) {
4191 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4194 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4197 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4200 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4203 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4206 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4216 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4219 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4222 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4225 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4228 if (rt2x00_rf(rt2x00dev, RF3070) ||
4229 rt2x00_rf(rt2x00dev, RF3290) ||
4230 rt2x00_rf(rt2x00dev, RF3322) ||
4231 rt2x00_rf(rt2x00dev, RF5350) ||
4232 rt2x00_rf(rt2x00dev, RF5360) ||
4233 rt2x00_rf(rt2x00dev, RF5362) ||
4234 rt2x00_rf(rt2x00dev, RF5370) ||
4235 rt2x00_rf(rt2x00dev, RF5372) ||
4236 rt2x00_rf(rt2x00dev, RF5390) ||
4237 rt2x00_rf(rt2x00dev, RF5392)) {
4238 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4239 if (rt2x00_rf(rt2x00dev, RF3322)) {
4250 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4252 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4254 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4261 if (rt2x00_rt(rt2x00dev, RT3352)) {
4262 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4263 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4264 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4266 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4267 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4268 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4269 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4270 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4271 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4272 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4275 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4277 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4281 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4283 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4285 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4286 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4287 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4288 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4289 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4290 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4291 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4292 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4294 if (rt2x00dev->default_ant.rx_chain_num > 1)
4295 rt2800_bbp_write(rt2x00dev, 86, 0x46);
4297 rt2800_bbp_write(rt2x00dev, 86, 0);
4299 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4300 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4301 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4302 if (rt2x00_rt(rt2x00dev, RT6352))
4303 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4305 rt2800_bbp_write(rt2x00dev, 86, 0);
4309 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4310 !rt2x00_rt(rt2x00dev, RT5392) &&
4311 !rt2x00_rt(rt2x00dev, RT6352)) {
4312 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4313 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4314 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4315 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4317 if (rt2x00_rt(rt2x00dev, RT3593))
4318 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4320 rt2800_bbp_write(rt2x00dev, 82, 0x84);
4321 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4323 if (rt2x00_rt(rt2x00dev, RT3593) ||
4324 rt2x00_rt(rt2x00dev, RT3883))
4325 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4329 if (rt2x00_rt(rt2x00dev, RT3572))
4330 rt2800_bbp_write(rt2x00dev, 82, 0x94);
4331 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4332 rt2x00_rt(rt2x00dev, RT3883))
4333 rt2800_bbp_write(rt2x00dev, 82, 0x82);
4334 else if (!rt2x00_rt(rt2x00dev, RT6352))
4335 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4337 if (rt2x00_rt(rt2x00dev, RT3593) ||
4338 rt2x00_rt(rt2x00dev, RT3883))
4339 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4341 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4342 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4344 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4347 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4351 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4353 if (rt2x00_rt(rt2x00dev, RT3572))
4354 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4356 if (rt2x00_rt(rt2x00dev, RT6352)) {
4357 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4363 switch (rt2x00dev->default_ant.tx_chain_num) {
4382 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4390 switch (rt2x00dev->default_ant.rx_chain_num) {
4411 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4413 if (rt2x00_rt(rt2x00dev, RT3572)) {
4414 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4418 reg = 0x1c + (2 * rt2x00dev->lna_gain);
4420 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4422 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4425 if (rt2x00_rt(rt2x00dev, RT3593)) {
4426 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4429 if (rt2x00_is_usb(rt2x00dev) ||
4430 rt2x00_is_pcie(rt2x00dev)) {
4440 if (rt2x00_is_usb(rt2x00dev)) {
4449 } else if (rt2x00_is_pcie(rt2x00dev)) {
4455 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4459 reg = 0x1c + 2 * rt2x00dev->lna_gain;
4461 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4463 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4468 if (rt2x00_rt(rt2x00dev, RT3883)) {
4470 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4472 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4476 reg = 0x2e + rt2x00dev->lna_gain;
4478 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4480 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4485 if (rt2x00_rt(rt2x00dev, RT5592)) {
4487 rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
4489 bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
4490 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4492 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4495 if (rt2x00_rt(rt2x00dev, RT6352)) {
4498 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
4500 rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
4503 rt2800_bbp_glrt_write(rt2x00dev, 157, bbp);
4505 if (rt2x00dev->default_ant.rx_chain_num == 1) {
4506 rt2800_bbp_write(rt2x00dev, 91, 0x07);
4507 rt2800_bbp_write(rt2x00dev, 95, 0x1a);
4508 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0);
4509 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12);
4510 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10);
4512 rt2800_bbp_write(rt2x00dev, 91, 0x06);
4513 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4514 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0);
4515 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
4516 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
4520 bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
4521 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4526 bbp = rt2800_bbp_read(rt2x00dev, 4);
4528 rt2800_bbp_write(rt2x00dev, 4, bbp);
4530 bbp = rt2800_bbp_read(rt2x00dev, 3);
4532 rt2800_bbp_write(rt2x00dev, 3, bbp);
4534 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4536 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4537 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4538 rt2800_bbp_write(rt2x00dev, 73, 0x16);
4540 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4541 rt2800_bbp_write(rt2x00dev, 70, 0x08);
4542 rt2800_bbp_write(rt2x00dev, 73, 0x11);
4551 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4552 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4553 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4558 if (rt2x00_rt(rt2x00dev, RT3352) ||
4559 rt2x00_rt(rt2x00dev, RT5350)) {
4560 bbp = rt2800_bbp_read(rt2x00dev, 49);
4562 rt2800_bbp_write(rt2x00dev, 49, bbp);
4566 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4577 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4589 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4590 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4596 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4602 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4608 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4614 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4621 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4627 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4633 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4639 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4645 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4662 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4683 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4691 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4697 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4727 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4732 if (rt2x00_has_cap_power_limit(rt2x00dev))
4748 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4758 if (rt2x00_rt(rt2x00dev, RT3593))
4761 if (rt2x00_rt(rt2x00dev, RT3883))
4764 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4772 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4778 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4819 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4836 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4843 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4847 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4852 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4863 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4874 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4885 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4895 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4900 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4911 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4922 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4932 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4937 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4948 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4959 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4970 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4980 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4985 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4996 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5007 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5018 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5028 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5033 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5044 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5055 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5066 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5076 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5081 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5092 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5103 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5113 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5118 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5129 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5140 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5149 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5157 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5162 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5171 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5172 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5173 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5174 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5175 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5176 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5177 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5178 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5179 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5180 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5182 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5184 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5186 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5188 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5190 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5194 rt2x00_dbg(rt2x00dev,
5197 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5205 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5217 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5220 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5238 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5256 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5273 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5276 rt2800_register_write(rt2x00dev,
5282 rt2800_register_write(rt2x00dev,
5300 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5305 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5308 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5312 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5315 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5319 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5322 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5324 rt2800_config_alc_rt6352(rt2x00dev, chan, power_level);
5338 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5352 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5361 switch (rt2x00dev->chip.rt) {
5369 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5381 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5401 r1 = rt2800_bbp_read(rt2x00dev, 1);
5403 rt2800_bbp_write(rt2x00dev, 1, r1);
5412 reg = rt2800_register_read(rt2x00dev, offset);
5415 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5427 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5438 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5449 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5460 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5465 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5477 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5488 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5499 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5510 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5514 rt2800_register_write(rt2x00dev, offset, reg);
5521 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5525 if (rt2x00_rt(rt2x00dev, RT3593) ||
5526 rt2x00_rt(rt2x00dev, RT3883))
5527 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5528 else if (rt2x00_rt(rt2x00dev, RT6352))
5529 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5531 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5534 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5536 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5537 rt2x00dev->tx_power);
5541 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5555 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5557 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5559 switch (rt2x00dev->chip.rf) {
5566 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5568 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5582 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5584 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5588 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5589 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5590 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5592 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5597 rt2x00dev->chip.rf);
5604 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5605 if (rt2x00dev->rf_channel <= 14) {
5606 switch (rt2x00dev->default_ant.tx_chain_num) {
5619 switch (rt2x00dev->default_ant.tx_chain_num) {
5632 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5636 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5641 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5646 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5649 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5658 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5660 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5665 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5667 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5669 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5673 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5675 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5679 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5684 rt2800_config_lna_gain(rt2x00dev, libconf);
5691 rt2800_update_survey(rt2x00dev);
5693 rt2800_config_channel(rt2x00dev, libconf->conf,
5695 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5699 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5702 rt2800_config_retry_limit(rt2x00dev, libconf);
5704 rt2800_config_ps(rt2x00dev, libconf);
5711 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5718 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5723 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5727 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5728 if (rt2x00_rt(rt2x00dev, RT3070) ||
5729 rt2x00_rt(rt2x00dev, RT3071) ||
5730 rt2x00_rt(rt2x00dev, RT3090) ||
5731 rt2x00_rt(rt2x00dev, RT3290) ||
5732 rt2x00_rt(rt2x00dev, RT3390) ||
5733 rt2x00_rt(rt2x00dev, RT3572) ||
5734 rt2x00_rt(rt2x00dev, RT3593) ||
5735 rt2x00_rt(rt2x00dev, RT5390) ||
5736 rt2x00_rt(rt2x00dev, RT5392) ||
5737 rt2x00_rt(rt2x00dev, RT5592) ||
5738 rt2x00_rt(rt2x00dev, RT6352))
5739 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5741 vgc = 0x2e + rt2x00dev->lna_gain;
5743 if (rt2x00_rt(rt2x00dev, RT3593) ||
5744 rt2x00_rt(rt2x00dev, RT3883))
5745 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5746 else if (rt2x00_rt(rt2x00dev, RT5592))
5747 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5749 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5750 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5752 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5759 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5763 if (rt2x00_rt(rt2x00dev, RT3572) ||
5764 rt2x00_rt(rt2x00dev, RT3593) ||
5765 rt2x00_rt(rt2x00dev, RT3883) ||
5766 rt2x00_rt(rt2x00dev, RT6352)) {
5767 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5769 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5770 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5771 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5773 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5781 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5783 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5787 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5792 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5800 vgc = rt2800_get_default_vgc(rt2x00dev);
5802 switch (rt2x00dev->chip.rt) {
5806 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5829 rt2800_set_vgc(rt2x00dev, qual, vgc);
5836 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5838 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5845 rt2800_disable_wpdma(rt2x00dev);
5847 ret = rt2800_drv_init_registers(rt2x00dev);
5851 if (rt2x00_rt(rt2x00dev, RT6352)) {
5852 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);
5854 bbp = rt2800_bbp_read(rt2x00dev, 21);
5856 rt2800_bbp_write(rt2x00dev, 21, bbp);
5857 bbp = rt2800_bbp_read(rt2x00dev, 21);
5859 rt2800_bbp_write(rt2x00dev, 21, bbp);
5861 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
5864 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5865 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5867 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5869 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5876 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5878 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5880 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5883 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5885 if (rt2x00_rt(rt2x00dev, RT3290)) {
5886 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5889 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5892 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5896 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5899 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5903 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5905 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5907 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5909 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5914 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5916 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5918 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5921 if (rt2x00_rt(rt2x00dev, RT3071) ||
5922 rt2x00_rt(rt2x00dev, RT3090) ||
5923 rt2x00_rt(rt2x00dev, RT3290) ||
5924 rt2x00_rt(rt2x00dev, RT3390)) {
5926 if (rt2x00_rt(rt2x00dev, RT3290))
5927 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5930 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5933 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5934 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5935 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5936 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5937 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5939 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5942 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5945 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5947 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5948 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5950 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5951 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5952 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5954 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5955 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5957 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5958 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5959 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5960 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5961 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5962 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5963 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5964 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5965 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5966 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5967 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5968 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5969 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5970 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5971 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5972 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5975 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5978 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5981 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5984 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5985 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5986 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5987 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5988 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5989 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5990 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5991 rt2x00_rt(rt2x00dev, RT5392)) {
5992 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5993 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5994 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5995 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5996 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5997 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5998 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5999 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
6000 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
6001 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
6002 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
6003 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
6004 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
6005 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
6006 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
6007 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
6008 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
6009 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
6010 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
6012 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
6014 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
6016 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
6018 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);
6019 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);
6020 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);
6021 rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);
6023 rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);
6026 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
6027 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
6030 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
6039 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
6041 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
6045 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
6047 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
6049 if (rt2x00_is_usb(rt2x00dev)) {
6051 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
6052 rt2x00_rt(rt2x00dev, RT2883) ||
6053 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
6061 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
6063 reg = rt2800_register_read(rt2x00dev, LED_CFG);
6071 rt2800_register_write(rt2x00dev, LED_CFG, reg);
6073 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
6075 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
6082 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
6084 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
6092 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
6094 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
6105 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6107 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
6118 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6120 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
6131 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6133 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
6144 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6146 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6157 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6159 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6170 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6172 if (rt2x00_is_usb(rt2x00dev)) {
6173 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6175 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6185 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6192 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6203 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6205 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6206 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6208 if (rt2x00_rt(rt2x00dev, RT3883)) {
6209 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6210 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6213 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6218 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6220 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6229 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6235 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6237 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6243 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6246 rt2800_config_wcid(rt2x00dev, NULL, i);
6247 rt2800_delete_wcid_attr(rt2x00dev, i);
6255 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6257 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6263 rt2800_clear_beacon_register(rt2x00dev, i);
6265 if (rt2x00_is_usb(rt2x00dev)) {
6266 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6268 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6269 } else if (rt2x00_is_pcie(rt2x00dev)) {
6270 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6272 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6273 } else if (rt2x00_is_soc(rt2x00dev)) {
6291 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6293 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6296 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6305 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6307 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6316 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6318 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6327 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6329 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6334 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6339 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6342 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6349 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6350 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6351 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6352 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6353 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6354 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6359 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6361 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6366 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6372 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6378 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6382 value = rt2800_bbp_read(rt2x00dev, 4);
6384 rt2800_bbp_write(rt2x00dev, 4, value);
6387 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6389 rt2800_bbp_write(rt2x00dev, 142, 1);
6390 rt2800_bbp_write(rt2x00dev, 143, 57);
6393 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6409 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6410 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6414 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6416 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6417 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6418 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6419 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6420 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6421 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6422 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6423 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6424 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6425 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6426 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6427 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6428 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6429 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6430 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6431 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6434 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6439 value = rt2800_bbp_read(rt2x00dev, 138);
6440 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6445 rt2800_bbp_write(rt2x00dev, 138, value);
6448 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6450 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6452 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6453 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6455 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6456 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6458 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6460 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6461 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6463 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6465 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6467 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6469 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6471 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6473 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6475 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6477 rt2800_bbp_write(rt2x00dev, 105, 0x01);
6479 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6482 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6484 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6485 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6487 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6488 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6489 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6491 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6492 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6495 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6497 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6499 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6501 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6503 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6504 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6506 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6508 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6510 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6512 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6514 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6516 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6518 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6521 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6523 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6524 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6526 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6527 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6529 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6531 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6532 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6533 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6535 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6537 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6539 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6541 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6543 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6545 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6547 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6548 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6549 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6550 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6552 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6554 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6556 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6558 if (rt2x00_rt(rt2x00dev, RT3071) ||
6559 rt2x00_rt(rt2x00dev, RT3090))
6560 rt2800_disable_unused_dac_adc(rt2x00dev);
6563 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6567 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6569 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6571 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6572 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6574 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6576 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6577 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6578 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6579 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6581 rt2800_bbp_write(rt2x00dev, 77, 0x58);
6583 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6585 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6586 rt2800_bbp_write(rt2x00dev, 79, 0x18);
6587 rt2800_bbp_write(rt2x00dev, 80, 0x09);
6588 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6590 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6592 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6594 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6596 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6598 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6600 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6602 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6604 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6606 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6608 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6610 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6612 rt2800_bbp_write(rt2x00dev, 67, 0x24);
6613 rt2800_bbp_write(rt2x00dev, 143, 0x04);
6614 rt2800_bbp_write(rt2x00dev, 142, 0x99);
6615 rt2800_bbp_write(rt2x00dev, 150, 0x30);
6616 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6617 rt2800_bbp_write(rt2x00dev, 152, 0x20);
6618 rt2800_bbp_write(rt2x00dev, 153, 0x34);
6619 rt2800_bbp_write(rt2x00dev, 154, 0x40);
6620 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6621 rt2800_bbp_write(rt2x00dev, 253, 0x04);
6623 value = rt2800_bbp_read(rt2x00dev, 47);
6625 rt2800_bbp_write(rt2x00dev, 47, value);
6628 value = rt2800_bbp_read(rt2x00dev, 3);
6631 rt2800_bbp_write(rt2x00dev, 3, value);
6634 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6636 rt2800_bbp_write(rt2x00dev, 3, 0x00);
6637 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6639 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6641 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6643 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6644 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6646 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6648 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6649 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6650 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6651 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6653 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6655 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6657 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6658 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6659 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6661 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6663 if (rt2x00_rt(rt2x00dev, RT5350)) {
6664 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6665 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6667 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6668 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6671 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6673 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6675 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6677 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6679 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6681 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6683 if (rt2x00_rt(rt2x00dev, RT5350)) {
6684 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6685 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6687 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6688 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6691 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6693 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6695 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6697 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6698 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6699 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6700 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6701 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6702 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6704 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6705 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6706 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6707 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6708 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6709 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6710 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6711 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6713 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6715 if (rt2x00_rt(rt2x00dev, RT5350)) {
6717 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6719 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6720 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6722 rt2800_bbp_write(rt2x00dev, 154, 0);
6726 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6728 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6729 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6731 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6732 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6734 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6736 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6737 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6738 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6740 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6742 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6744 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6746 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6748 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6750 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6752 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6753 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6755 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6757 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6759 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6761 rt2800_disable_unused_dac_adc(rt2x00dev);
6764 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6766 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6768 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6769 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6771 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6772 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6774 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6776 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6777 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6778 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6780 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6782 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6784 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6786 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6788 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6790 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6792 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6794 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6796 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6798 rt2800_disable_unused_dac_adc(rt2x00dev);
6801 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6803 rt2800_init_bbp_early(rt2x00dev);
6805 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6806 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6807 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6808 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6810 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6813 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6814 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6817 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6819 rt2800_init_bbp_early(rt2x00dev);
6821 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6822 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6824 rt2800_bbp_write(rt2x00dev, 86, 0x46);
6825 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6827 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6829 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6830 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6831 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6832 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6833 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6834 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6835 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6838 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6839 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6840 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6841 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6842 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6844 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6847 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6848 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6849 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6850 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6851 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6852 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6853 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6854 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6855 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6858 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6864 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6866 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6868 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6869 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6871 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6873 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6874 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6875 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6876 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6878 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6880 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6882 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6883 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6884 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6886 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6888 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6890 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6892 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6894 if (rt2x00_rt(rt2x00dev, RT5392))
6895 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6897 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6899 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6901 if (rt2x00_rt(rt2x00dev, RT5392)) {
6902 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6903 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6906 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6908 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6910 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6912 if (rt2x00_rt(rt2x00dev, RT5390))
6913 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6914 else if (rt2x00_rt(rt2x00dev, RT5392))
6915 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6919 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6921 if (rt2x00_rt(rt2x00dev, RT5392)) {
6922 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6923 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6926 rt2800_disable_unused_dac_adc(rt2x00dev);
6928 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6934 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6937 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6946 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6950 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6951 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6952 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6953 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6954 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6957 value = rt2800_bbp_read(rt2x00dev, 152);
6962 rt2800_bbp_write(rt2x00dev, 152, value);
6964 rt2800_init_freq_calibration(rt2x00dev);
6967 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6973 rt2800_init_bbp_early(rt2x00dev);
6975 value = rt2800_bbp_read(rt2x00dev, 105);
6977 rt2x00dev->default_ant.rx_chain_num == 2);
6978 rt2800_bbp_write(rt2x00dev, 105, value);
6980 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6982 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6983 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6984 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6985 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6986 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6987 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6988 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6989 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6990 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6991 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6992 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6993 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6994 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6995 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6996 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6997 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6998 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6999 rt2800_bbp_write(rt2x00dev, 98, 0x12);
7000 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7001 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7003 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7004 rt2800_bbp_write(rt2x00dev, 106, 0x35);
7005 rt2800_bbp_write(rt2x00dev, 128, 0x12);
7006 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
7007 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
7008 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
7011 rt2800_init_bbp_5592_glrt(rt2x00dev);
7013 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7015 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7018 value = rt2800_bbp_read(rt2x00dev, 152);
7026 rt2800_bbp_write(rt2x00dev, 152, value);
7028 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
7029 value = rt2800_bbp_read(rt2x00dev, 254);
7031 rt2800_bbp_write(rt2x00dev, 254, value);
7034 rt2800_init_freq_calibration(rt2x00dev);
7036 rt2800_bbp_write(rt2x00dev, 84, 0x19);
7037 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7038 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7041 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
7046 bbp = rt2800_bbp_read(rt2x00dev, 105);
7048 rt2x00dev->default_ant.rx_chain_num == 2);
7049 rt2800_bbp_write(rt2x00dev, 105, bbp);
7052 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7055 bbp = rt2800_bbp_read(rt2x00dev, 1);
7057 rt2800_bbp_write(rt2x00dev, 1, bbp);
7060 rt2800_bbp_write(rt2x00dev, 3, 0x08);
7061 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
7062 rt2800_bbp_write(rt2x00dev, 6, 0x08);
7063 rt2800_bbp_write(rt2x00dev, 14, 0x09);
7064 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
7065 rt2800_bbp_write(rt2x00dev, 16, 0x01);
7066 rt2800_bbp_write(rt2x00dev, 20, 0x06);
7067 rt2800_bbp_write(rt2x00dev, 21, 0x00);
7068 rt2800_bbp_write(rt2x00dev, 22, 0x00);
7069 rt2800_bbp_write(rt2x00dev, 27, 0x00);
7070 rt2800_bbp_write(rt2x00dev, 28, 0x00);
7071 rt2800_bbp_write(rt2x00dev, 30, 0x00);
7072 rt2800_bbp_write(rt2x00dev, 31, 0x48);
7073 rt2800_bbp_write(rt2x00dev, 47, 0x40);
7074 rt2800_bbp_write(rt2x00dev, 62, 0x00);
7075 rt2800_bbp_write(rt2x00dev, 63, 0x00);
7076 rt2800_bbp_write(rt2x00dev, 64, 0x00);
7077 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
7078 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
7079 rt2800_bbp_write(rt2x00dev, 67, 0x20);
7080 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
7081 rt2800_bbp_write(rt2x00dev, 69, 0x10);
7082 rt2800_bbp_write(rt2x00dev, 70, 0x05);
7083 rt2800_bbp_write(rt2x00dev, 73, 0x18);
7084 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
7085 rt2800_bbp_write(rt2x00dev, 75, 0x60);
7086 rt2800_bbp_write(rt2x00dev, 76, 0x44);
7087 rt2800_bbp_write(rt2x00dev, 77, 0x59);
7088 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
7089 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
7090 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
7091 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
7092 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
7093 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
7094 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
7095 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7096 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7097 rt2800_bbp_write(rt2x00dev, 91, 0x04);
7098 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7099 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
7100 rt2800_bbp_write(rt2x00dev, 96, 0x00);
7101 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7102 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7104 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7105 rt2800_bbp_write(rt2x00dev, 106, 0x12);
7106 rt2800_bbp_write(rt2x00dev, 109, 0x00);
7107 rt2800_bbp_write(rt2x00dev, 134, 0x10);
7108 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7109 rt2800_bbp_write(rt2x00dev, 137, 0x04);
7110 rt2800_bbp_write(rt2x00dev, 142, 0x30);
7111 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7112 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7113 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7114 rt2800_bbp_write(rt2x00dev, 162, 0x77);
7115 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7116 rt2800_bbp_write(rt2x00dev, 164, 0x00);
7117 rt2800_bbp_write(rt2x00dev, 165, 0x00);
7118 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7119 rt2800_bbp_write(rt2x00dev, 187, 0x00);
7120 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7121 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7122 rt2800_bbp_write(rt2x00dev, 187, 0x01);
7123 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7124 rt2800_bbp_write(rt2x00dev, 189, 0x00);
7126 rt2800_bbp_write(rt2x00dev, 91, 0x06);
7127 rt2800_bbp_write(rt2x00dev, 92, 0x04);
7128 rt2800_bbp_write(rt2x00dev, 93, 0x54);
7129 rt2800_bbp_write(rt2x00dev, 99, 0x50);
7130 rt2800_bbp_write(rt2x00dev, 148, 0x84);
7131 rt2800_bbp_write(rt2x00dev, 167, 0x80);
7132 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7133 rt2800_bbp_write(rt2x00dev, 106, 0x13);
7136 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7137 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7138 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7139 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7140 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7141 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7142 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7143 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7144 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7145 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7146 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7147 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7148 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7149 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7150 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7151 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7152 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7153 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7154 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7155 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7156 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7157 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7158 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7159 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7160 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7161 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7162 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7163 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7164 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7165 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7166 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7167 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7168 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7169 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7170 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7171 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7172 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7173 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7174 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7175 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7176 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7177 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7178 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7179 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7180 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7181 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7182 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7183 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7184 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7185 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7186 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7187 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7188 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7189 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7190 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7191 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7192 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7193 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7194 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7195 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7196 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7197 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7198 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7199 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7200 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7201 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7202 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7203 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7204 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7205 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7206 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7207 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7208 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7209 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7210 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7211 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7212 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7213 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7214 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7215 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7216 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7217 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7218 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7221 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7222 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7223 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7224 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7225 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7226 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7227 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7228 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7229 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7230 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7231 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7232 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7233 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7234 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7235 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7236 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7237 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7238 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7239 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7240 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7242 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7244 rt2800_bbp_write(rt2x00dev, 84, 0x19);
7247 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7254 if (rt2800_is_305x_soc(rt2x00dev))
7255 rt2800_init_bbp_305x_soc(rt2x00dev);
7257 switch (rt2x00dev->chip.rt) {
7261 rt2800_init_bbp_28xx(rt2x00dev);
7266 rt2800_init_bbp_30xx(rt2x00dev);
7269 rt2800_init_bbp_3290(rt2x00dev);
7273 rt2800_init_bbp_3352(rt2x00dev);
7276 rt2800_init_bbp_3390(rt2x00dev);
7279 rt2800_init_bbp_3572(rt2x00dev);
7282 rt2800_init_bbp_3593(rt2x00dev);
7285 rt2800_init_bbp_3883(rt2x00dev);
7289 rt2800_init_bbp_53xx(rt2x00dev);
7292 rt2800_init_bbp_5592(rt2x00dev);
7295 rt2800_init_bbp_6352(rt2x00dev);
7300 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7306 rt2800_bbp_write(rt2x00dev, reg_id, value);
7311 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7315 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7317 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7320 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7331 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7333 bbp = rt2800_bbp_read(rt2x00dev, 4);
7335 rt2800_bbp_write(rt2x00dev, 4, bbp);
7337 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7339 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7341 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7343 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7348 rt2800_bbp_write(rt2x00dev, 24, 0);
7351 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7354 passband = rt2800_bbp_read(rt2x00dev, 55);
7362 rt2800_bbp_write(rt2x00dev, 24, 0x06);
7365 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7368 stopband = rt2800_bbp_read(rt2x00dev, 55);
7376 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7381 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7385 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7390 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7392 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7395 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7398 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7400 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7408 if (rt2x00_rt(rt2x00dev, RT3070)) {
7417 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7419 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7424 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7425 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7430 rt2800_bbp_write(rt2x00dev, 24, 0);
7432 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7434 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7439 bbp = rt2800_bbp_read(rt2x00dev, 4);
7441 rt2800_bbp_write(rt2x00dev, 4, bbp);
7444 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7446 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7450 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7453 if (rt2x00_rt(rt2x00dev, RT3070) ||
7454 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7455 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7456 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7457 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7461 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7467 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7469 if (rt2x00_rt(rt2x00dev, RT3090)) {
7471 bbp = rt2800_bbp_read(rt2x00dev, 138);
7472 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7477 rt2800_bbp_write(rt2x00dev, 138, bbp);
7480 if (rt2x00_rt(rt2x00dev, RT3070)) {
7481 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7482 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7489 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7490 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7491 rt2x00_rt(rt2x00dev, RT3090) ||
7492 rt2x00_rt(rt2x00dev, RT3390)) {
7493 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7499 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7501 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7503 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7505 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7507 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7509 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7511 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7515 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7517 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7521 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7523 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7525 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7529 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7531 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7533 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7535 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7537 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7539 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7542 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7544 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7546 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7551 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7557 reg = rt2800_bbp_read(rt2x00dev, 138);
7558 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7563 rt2800_bbp_write(rt2x00dev, 138, reg);
7565 reg = rt2800_rfcsr_read(rt2x00dev, 38);
7567 rt2800_rfcsr_write(rt2x00dev, 38, reg);
7569 reg = rt2800_rfcsr_read(rt2x00dev, 39);
7571 rt2800_rfcsr_write(rt2x00dev, 39, reg);
7573 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7575 reg = rt2800_rfcsr_read(rt2x00dev, 30);
7577 rt2800_rfcsr_write(rt2x00dev, 30, reg);
7580 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7582 rt2800_rf_init_calibration(rt2x00dev, 30);
7584 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7585 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7586 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7587 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7588 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7589 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7590 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7591 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7592 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7593 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7594 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7595 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7596 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7597 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7598 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7599 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7600 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7601 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7602 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7603 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7604 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7605 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7606 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7607 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7608 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7609 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7610 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7611 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7612 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7613 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7614 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7615 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7618 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7625 rt2800_rf_init_calibration(rt2x00dev, 30);
7627 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7628 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7629 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7630 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7631 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7632 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7633 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7634 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7635 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7636 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7637 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7638 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7639 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7640 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7641 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7642 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7643 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7644 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7645 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7647 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7648 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7651 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7652 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7653 rt2x00_rt(rt2x00dev, RT3090)) {
7654 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7656 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7658 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7660 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7662 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7663 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7664 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7670 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7672 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7674 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7677 rt2800_rx_filter_calibration(rt2x00dev);
7679 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7680 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7681 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7682 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7684 rt2800_led_open_drain_enable(rt2x00dev);
7685 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7688 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7692 rt2800_rf_init_calibration(rt2x00dev, 2);
7694 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7695 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7696 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7697 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7698 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7699 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7700 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7701 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7702 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7703 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7704 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7705 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7706 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7707 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7708 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7709 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7710 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7711 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7712 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7713 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7714 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7715 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7716 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7717 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7718 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7719 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7720 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7721 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7722 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7723 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7724 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7725 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7726 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7727 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7728 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7729 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7730 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7731 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7732 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7733 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7734 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7735 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7736 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7737 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7738 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7739 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7741 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7743 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7745 rt2800_led_open_drain_enable(rt2x00dev);
7746 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7749 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7752 &rt2x00dev->cap_flags);
7754 &rt2x00dev->cap_flags);
7757 rt2800_rf_init_calibration(rt2x00dev, 30);
7759 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7760 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7761 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7762 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7763 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7764 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7765 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7766 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7767 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7768 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7769 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7770 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7771 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7772 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7773 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7774 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7775 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7776 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7777 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7778 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7779 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7780 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7781 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7782 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7783 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7784 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7785 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7786 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7787 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7788 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7789 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7790 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7791 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7797 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7798 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7799 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7800 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7801 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7802 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7803 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7809 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7815 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7816 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7817 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7818 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7819 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7820 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7821 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7822 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7828 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7829 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7830 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7831 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7832 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7833 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7834 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7835 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7836 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7837 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7838 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7839 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7840 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7841 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7843 rt2800_rx_filter_calibration(rt2x00dev);
7844 rt2800_led_open_drain_enable(rt2x00dev);
7845 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7848 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7852 rt2800_rf_init_calibration(rt2x00dev, 30);
7854 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7855 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7856 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7857 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7858 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7859 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7860 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7861 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7862 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7863 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7864 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7865 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7866 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7867 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7868 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7869 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7870 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7871 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7872 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7873 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7874 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7875 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7876 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7877 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7878 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7879 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7880 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7881 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7882 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7883 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7884 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7885 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7887 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7889 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7891 rt2800_rx_filter_calibration(rt2x00dev);
7893 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7894 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7896 rt2800_led_open_drain_enable(rt2x00dev);
7897 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7900 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7905 rt2800_rf_init_calibration(rt2x00dev, 30);
7907 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7908 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7909 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7910 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7911 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7912 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7913 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7914 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7915 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7916 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7917 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7918 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7919 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7920 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7921 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7922 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7923 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7924 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7925 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7926 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7927 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7928 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7929 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7930 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7931 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7932 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7933 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7934 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7935 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7936 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7937 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7939 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7941 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7943 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7946 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7948 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7951 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7953 rt2800_rx_filter_calibration(rt2x00dev);
7954 rt2800_led_open_drain_enable(rt2x00dev);
7955 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7958 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7963 bbp = rt2800_bbp_read(rt2x00dev, 105);
7964 if (rt2x00dev->default_ant.rx_chain_num == 1)
7968 rt2800_bbp_write(rt2x00dev, 105, bbp);
7970 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7972 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7973 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7974 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7975 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7976 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7977 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7978 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7979 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7982 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7984 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7987 rt2800_bbp_write(rt2x00dev, 142, 6);
7988 rt2800_bbp_write(rt2x00dev, 143, 160);
7989 rt2800_bbp_write(rt2x00dev, 142, 7);
7990 rt2800_bbp_write(rt2x00dev, 143, 161);
7991 rt2800_bbp_write(rt2x00dev, 142, 8);
7992 rt2800_bbp_write(rt2x00dev, 143, 162);
7995 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7998 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
8001 rt2800_bbp_write(rt2x00dev, 105, 0x04);
8005 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
8007 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8012 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
8015 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
8018 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8019 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
8020 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8021 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8022 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8023 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8024 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8025 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
8026 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
8027 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8028 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8029 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8030 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8031 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8032 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
8033 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
8034 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
8035 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
8036 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8037 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8038 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
8039 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8040 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8041 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8042 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8043 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
8044 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
8045 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
8046 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
8047 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
8048 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8049 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
8053 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8055 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8057 rt2800_freq_cal_mode1(rt2x00dev);
8059 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
8061 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
8063 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8066 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8068 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8070 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8077 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
8078 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
8080 rt2800_led_open_drain_enable(rt2x00dev);
8081 rt2800_normal_mode_setup_3593(rt2x00dev);
8083 rt3593_post_bbp_init(rt2x00dev);
8088 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
8090 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
8091 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
8092 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8093 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8094 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
8095 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8096 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8097 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8098 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8099 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8100 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8101 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8102 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8103 if (rt2800_clk_is_20mhz(rt2x00dev))
8104 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8106 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8107 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8108 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8109 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8110 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8111 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8112 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8113 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8114 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8115 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8116 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8117 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8118 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8119 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8120 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8121 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8122 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8123 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8124 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8125 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8126 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8127 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8128 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8129 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8130 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8131 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8132 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8133 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8134 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8135 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8136 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8137 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8138 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8139 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8140 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8141 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8142 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8143 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8144 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8145 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8146 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8147 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8148 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8149 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8150 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8151 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8152 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8153 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8154 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8155 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8158 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8165 rt2800_rf_init_calibration(rt2x00dev, 2);
8167 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8168 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8169 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8170 rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8171 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8172 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8173 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8174 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8175 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8176 rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8177 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8178 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8179 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8180 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8181 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8182 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8183 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8189 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8190 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8191 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8192 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8193 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8194 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8195 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8196 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8197 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8198 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8199 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8200 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8201 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8202 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8203 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8204 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8205 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8206 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8207 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8208 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8209 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8210 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8211 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8212 rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8213 rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8214 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8215 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8216 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8217 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8218 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8219 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8220 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8221 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8222 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8223 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8224 rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8225 rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8226 rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8227 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8228 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8229 rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8230 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8231 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8232 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8233 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8234 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8238 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8240 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8242 rt2800_bbp_write(rt2x00dev, 105, 0x05);
8244 rt2800_bbp_write(rt2x00dev, 179, 0x02);
8245 rt2800_bbp_write(rt2x00dev, 180, 0x00);
8246 rt2800_bbp_write(rt2x00dev, 182, 0x40);
8247 rt2800_bbp_write(rt2x00dev, 180, 0x01);
8248 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8250 rt2800_bbp_write(rt2x00dev, 179, 0x00);
8252 rt2800_bbp_write(rt2x00dev, 142, 0x04);
8253 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8254 rt2800_bbp_write(rt2x00dev, 142, 0x06);
8255 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8256 rt2800_bbp_write(rt2x00dev, 142, 0x07);
8257 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8258 rt2800_bbp_write(rt2x00dev, 142, 0x08);
8259 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8260 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8263 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8264 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8267 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8270 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8273 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8277 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8279 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8281 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8283 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8285 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8287 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8289 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8291 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8293 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8296 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8298 rt2800_rf_init_calibration(rt2x00dev, 2);
8300 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8301 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8302 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8303 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8304 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8305 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8307 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8308 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8309 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8310 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8311 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8312 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8313 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8314 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8315 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8316 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8317 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8319 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8320 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8321 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8322 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8323 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8324 if (rt2x00_is_usb(rt2x00dev) &&
8325 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8326 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8328 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8329 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8330 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8331 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8332 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8334 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8335 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8336 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8337 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8338 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8339 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8340 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8341 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8342 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8343 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8345 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8346 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8347 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8348 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8349 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8350 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8351 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8352 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8354 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8355 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8356 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8357 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8359 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8360 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8361 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8363 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8364 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8365 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8366 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8367 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8369 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8370 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8371 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8372 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8374 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8375 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8376 if (rt2x00_is_usb(rt2x00dev))
8377 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8379 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8381 if (rt2x00_is_usb(rt2x00dev))
8382 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8384 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8386 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8387 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8389 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8391 rt2800_led_open_drain_enable(rt2x00dev);
8394 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8396 rt2800_rf_init_calibration(rt2x00dev, 2);
8398 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8399 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8400 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8401 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8402 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8403 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8404 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8405 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8406 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8407 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8408 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8409 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8410 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8411 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8412 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8413 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8414 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8415 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8416 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8417 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8418 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8419 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8420 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8421 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8422 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8423 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8424 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8425 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8426 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8427 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8428 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8429 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8430 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8431 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8432 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8433 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8434 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8435 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8436 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8437 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8438 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8439 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8440 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8441 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8442 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8443 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8444 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8445 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8446 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8447 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8448 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8449 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8450 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8451 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8452 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8453 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8454 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8455 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8457 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8459 rt2800_led_open_drain_enable(rt2x00dev);
8462 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8464 rt2800_rf_init_calibration(rt2x00dev, 30);
8466 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8467 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8468 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8469 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8470 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8471 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8472 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8473 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8474 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8475 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8476 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8477 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8478 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8479 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8480 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8481 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8482 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8483 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8484 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8485 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8486 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8488 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8491 rt2800_freq_cal_mode1(rt2x00dev);
8494 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8495 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8497 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8499 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8500 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8502 rt2800_led_open_drain_enable(rt2x00dev);
8505 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
8511 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8512 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8513 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
8514 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
8516 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8517 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8519 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
8520 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
8521 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
8522 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
8523 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8524 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8526 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
8529 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8533 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
8535 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
8538 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8542 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
8544 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8545 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8546 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
8547 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
8548 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
8549 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
8552 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
8563 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
8578 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8579 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
8580 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
8581 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8582 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8583 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8584 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8585 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8587 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
8588 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
8589 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
8591 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8592 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8593 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8594 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
8596 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8598 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8600 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8601 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
8603 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8605 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8607 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
8608 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
8611 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
8613 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
8615 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
8616 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
8617 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
8618 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
8619 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
8621 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
8622 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
8623 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
8625 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
8627 rt2800_bbp_write(rt2x00dev, 47, 0x04);
8628 rt2800_bbp_write(rt2x00dev, 22, 0x80);
8630 bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8635 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8636 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8638 rt2800_bbp_write(rt2x00dev, 22, 0x80);
8640 bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8645 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8647 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
8653 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
8655 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8657 bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8659 rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8660 bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8662 rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8664 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
8665 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
8666 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
8667 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8668 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8669 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8670 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8671 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8673 rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
8674 rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
8675 rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
8677 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8678 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8680 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
8681 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
8684 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
8691 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8694 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
8696 rt2800_bbp_write(rt2x00dev, 158, 141);
8697 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8699 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8701 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8702 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
8704 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8705 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
8707 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8708 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8711 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
8712 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8713 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
8715 rt2800_bbp_write(rt2x00dev, 158, 140);
8716 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8718 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8720 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8723 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8729 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8731 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8733 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
8735 rt2800_bbp_write(rt2x00dev, 158, 141);
8736 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8738 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8740 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
8760 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
8788 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8789 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8790 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8791 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
8792 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
8793 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
8794 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
8796 bbp1 = rt2800_bbp_read(rt2x00dev, 1);
8797 bbp4 = rt2800_bbp_read(rt2x00dev, 4);
8799 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
8801 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
8802 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
8806 rt2800_bbp_write(rt2x00dev, 4, bbpval);
8808 bbpval = rt2800_bbp_read(rt2x00dev, 21);
8810 rt2800_bbp_write(rt2x00dev, 21, bbpval);
8812 rt2800_bbp_write(rt2x00dev, 21, bbpval);
8814 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
8815 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
8816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
8817 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
8819 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
8821 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
8823 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8824 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8825 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
8826 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
8827 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
8828 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8829 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8830 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8831 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8832 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8833 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8835 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
8836 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
8837 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
8838 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8839 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
8840 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
8841 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
8842 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
8844 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
8845 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
8846 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
8847 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
8848 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
8849 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
8850 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
8851 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8853 rt2800_bbp_write(rt2x00dev, 23, 0x0);
8854 rt2800_bbp_write(rt2x00dev, 24, 0x0);
8856 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
8858 bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
8859 bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
8861 rt2800_bbp_write(rt2x00dev, 241, 0x10);
8862 rt2800_bbp_write(rt2x00dev, 242, 0x84);
8863 rt2800_bbp_write(rt2x00dev, 244, 0x31);
8865 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
8867 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
8869 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
8871 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
8873 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
8874 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8876 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
8877 rt2800_bbp_write(rt2x00dev, 23, 0x06);
8878 rt2800_bbp_write(rt2x00dev, 24, 0x06);
8880 rt2800_bbp_write(rt2x00dev, 23, 0x02);
8881 rt2800_bbp_write(rt2x00dev, 24, 0x02);
8887 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8889 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8891 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8893 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8898 rt2800_bbp_write(rt2x00dev, 1, bbpval);
8900 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
8903 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8905 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8907 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8909 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
8914 rt2800_bbp_write(rt2x00dev, 1, bbpval);
8916 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
8922 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
8923 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
8925 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
8928 bbpval = rt2800_bbp_read(rt2x00dev, 159);
8936 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
8944 rt2800_bbp_write(rt2x00dev, 158, 0x1e);
8945 rt2800_bbp_write(rt2x00dev, 159, i);
8946 rt2800_bbp_write(rt2x00dev, 158, 0x22);
8947 value = rt2800_bbp_read(rt2x00dev, 159);
8949 rt2800_bbp_write(rt2x00dev, 158, 0x21);
8950 value = rt2800_bbp_read(rt2x00dev, 159);
8952 rt2800_bbp_write(rt2x00dev, 158, 0x20);
8953 value = rt2800_bbp_read(rt2x00dev, 159);
8955 rt2800_bbp_write(rt2x00dev, 158, 0x1f);
8956 value = rt2800_bbp_read(rt2x00dev, 159);
8977 rt2x00_dbg(rt2x00dev,
9008 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
9016 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9025 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9030 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9035 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9037 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9041 rt2800_bbp_write(rt2x00dev, 158, 0x37);
9042 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9043 rt2800_bbp_write(rt2x00dev, 158, 0x35);
9044 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9046 rt2800_bbp_write(rt2x00dev, 158, 0x55);
9047 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9048 rt2800_bbp_write(rt2x00dev, 158, 0x53);
9049 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9054 rt2800_bbp_write(rt2x00dev, 158, 0x3);
9055 bbpval = rt2800_bbp_read(rt2x00dev, 159);
9056 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
9058 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9059 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9060 rt2800_bbp_write(rt2x00dev, 1, bbp1);
9061 rt2800_bbp_write(rt2x00dev, 4, bbp4);
9062 rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9063 rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9065 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9066 bbpval = rt2800_bbp_read(rt2x00dev, 21);
9068 rt2800_bbp_write(rt2x00dev, 21, bbpval);
9071 rt2800_bbp_write(rt2x00dev, 21, bbpval);
9073 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
9074 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
9075 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9077 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
9078 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
9079 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
9080 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
9081 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
9082 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
9083 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
9084 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
9086 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
9087 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
9088 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
9089 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
9090 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
9091 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
9092 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
9093 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
9095 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
9097 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9099 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
9101 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
9102 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
9103 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
9104 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
9105 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
9106 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9109 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
9115 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9119 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9123 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9127 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9131 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
9135 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
9139 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
9143 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
9147 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
9151 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
9155 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
9159 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
9163 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
9168 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9172 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9176 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9180 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9184 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
9188 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
9192 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
9196 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
9200 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
9204 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
9208 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
9212 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
9216 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
9221 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
9225 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
9236 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
9237 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
9243 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
9245 rt2800_bbp_write(rt2x00dev, 158, 0xAA);
9246 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9248 rt2800_bbp_write(rt2x00dev, 158, 0xAB);
9249 rt2800_bbp_write(rt2x00dev, 159, 0x0A);
9251 rt2800_bbp_write(rt2x00dev, 158, 0xAC);
9252 rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9254 rt2800_bbp_write(rt2x00dev, 158, 0xAD);
9255 rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9257 rt2800_bbp_write(rt2x00dev, 244, 0x40);
9260 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
9268 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9269 rt2800_bbp_write(rt2x00dev, 159, 0x9b);
9275 bbp = rt2800_bbp_read(rt2x00dev, 159);
9279 rt2800_bbp_write(rt2x00dev, 158, 0xba);
9280 rt2800_bbp_write(rt2x00dev, 159, tidx);
9281 rt2800_bbp_write(rt2x00dev, 159, tidx);
9282 rt2800_bbp_write(rt2x00dev, 159, tidx);
9284 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9293 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
9299 rt2800_bbp_write(rt2x00dev, 158, 0xba);
9300 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9301 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9302 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9304 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9319 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
9325 rt2800_bbp_write(rt2x00dev, 158, 0xBA);
9326 rt2800_bbp_write(rt2x00dev, 159, tidx);
9327 rt2800_bbp_write(rt2x00dev, 159, tidx);
9328 rt2800_bbp_write(rt2x00dev, 159, tidx);
9330 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9343 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
9347 rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9349 rt2800_bbp_write(rt2x00dev, 159, bbp);
9356 rt2800_bbp_write(rt2x00dev, 158, bbp);
9358 rt2800_bbp_write(rt2x00dev, 159, bbp);
9361 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
9371 rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9372 rt2800_bbp_write(rt2x00dev, 159, 0x80);
9382 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
9383 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9388 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
9389 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9391 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
9393 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
9405 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
9408 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
9416 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
9451 rt2800_bbp_write(rt2x00dev, 158, bbp);
9452 rt2800_bbp_write(rt2x00dev, 159, idx0);
9454 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9463 rt2800_bbp_write(rt2x00dev, 158, bbp);
9464 rt2800_bbp_write(rt2x00dev, 159, idx1);
9466 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9468 rt2x00_dbg(rt2x00dev,
9485 rt2800_bbp_write(rt2x00dev, 158, bbp);
9486 rt2800_bbp_write(rt2x00dev, 159, iq_err);
9493 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
9515 rt2800_bbp_write(rt2x00dev, 158, bbp);
9516 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
9519 rt2800_bbp_write(rt2x00dev, 158, bbp);
9520 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
9522 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9532 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
9540 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
9542 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
9543 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
9544 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9545 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
9546 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
9547 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
9548 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
9549 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
9550 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
9551 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
9552 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
9553 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
9554 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
9557 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
9559 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
9560 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
9561 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9562 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
9563 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
9564 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
9565 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
9566 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
9567 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
9568 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
9569 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
9570 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
9571 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
9574 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
9608 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9609 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9610 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9611 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9612 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9613 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9614 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9615 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
9616 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
9618 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9620 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9622 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9623 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9625 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9627 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9629 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9630 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9633 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9635 bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
9636 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
9637 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9639 rt2800_bbp_write(rt2x00dev, 30, 0x1F);
9640 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
9641 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
9643 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9644 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9646 rt2800_setbbptonegenerator(rt2x00dev);
9649 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9650 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9651 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
9652 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9653 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9654 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9655 rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
9659 rt2800_rf_aux_tx0_loopback(rt2x00dev);
9661 rt2800_rf_aux_tx1_loopback(rt2x00dev);
9666 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9668 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9670 rt2800_bbp_write(rt2x00dev, 158, 0x05);
9671 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9673 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9675 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9677 rt2800_bbp_write(rt2x00dev, 159, 0x01);
9681 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
9682 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
9684 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9688 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
9690 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
9693 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
9697 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9698 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9699 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9700 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9701 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9702 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
9703 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9704 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
9709 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9710 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9712 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9718 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9719 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9721 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
9727 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9729 rt2800_bbp_write(rt2x00dev, 159, bbp);
9730 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
9732 rt2800_bbp_write(rt2x00dev, 158, 0xb1);
9735 rt2800_bbp_write(rt2x00dev, 159, bbp);
9736 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
9738 rt2800_bbp_write(rt2x00dev, 158, 0xb2);
9741 rt2800_bbp_write(rt2x00dev, 159, bbp);
9742 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
9744 rt2800_bbp_write(rt2x00dev, 158, 0xb8);
9747 rt2800_bbp_write(rt2x00dev, 159, bbp);
9748 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
9750 rt2800_bbp_write(rt2x00dev, 158, 0xb9);
9753 rt2800_bbp_write(rt2x00dev, 159, bbp);
9754 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
9758 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9759 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9761 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9763 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9764 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9767 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9769 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9771 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9773 rt2800_rf_configrecover(rt2x00dev, rf_store);
9775 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9776 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9777 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9778 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9779 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9781 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9782 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9783 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9784 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9785 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
9786 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
9787 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9789 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9790 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9791 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9792 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9793 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9794 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9796 bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
9797 bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
9798 bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
9799 bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
9800 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9802 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9804 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9806 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9807 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9809 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9811 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9813 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9814 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9817 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
9818 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9821 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9822 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9824 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9825 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
9826 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9828 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9830 rt2800_bbp_write(rt2x00dev, 241, 0x14);
9831 rt2800_bbp_write(rt2x00dev, 242, 0x80);
9832 rt2800_bbp_write(rt2x00dev, 244, 0x31);
9834 rt2800_setbbptonegenerator(rt2x00dev);
9837 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9838 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9841 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9843 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9844 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
9845 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9848 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
9851 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9853 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
9854 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
9856 rt2800_bbp_write(rt2x00dev, 158, 0x03);
9857 rt2800_bbp_write(rt2x00dev, 159, 0x60);
9858 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9859 rt2800_bbp_write(rt2x00dev, 159, 0x80);
9862 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9863 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9866 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9867 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9868 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9871 rt2800_bbp_write(rt2x00dev, 1, bbp);
9873 rt2800_rf_aux_tx0_loopback(rt2x00dev);
9874 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9876 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9877 rt2800_bbp_write(rt2x00dev, 159, 0x01);
9878 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
9881 rt2800_bbp_write(rt2x00dev, 1, bbp);
9883 rt2800_rf_aux_tx1_loopback(rt2x00dev);
9884 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9887 rt2800_bbp_write(rt2x00dev, 158, 0x05);
9888 rt2800_bbp_write(rt2x00dev, 159, 0x04);
9891 rt2800_bbp_write(rt2x00dev, 158, bbp);
9892 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9894 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9895 rt2800_bbp_write(rt2x00dev, 23, 0x06);
9896 rt2800_bbp_write(rt2x00dev, 24, 0x06);
9899 rt2800_bbp_write(rt2x00dev, 23, 0x1F);
9900 rt2800_bbp_write(rt2x00dev, 24, 0x1F);
9906 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9907 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9910 rt2800_bbp_write(rt2x00dev, 158, bbp);
9911 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9912 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9913 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9914 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9917 rt2800_bbp_write(rt2x00dev, 158, bbp);
9918 rt2800_bbp_write(rt2x00dev, 159, 0x21);
9919 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9920 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
9921 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9923 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
9925 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9926 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
9940 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9944 rt2800_bbp_write(rt2x00dev, 158, bbp);
9945 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9947 rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
9950 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9951 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9952 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9954 rt2800_bbp_write(rt2x00dev, 158, 0x28);
9956 rt2800_bbp_write(rt2x00dev, 159, bbp);
9958 rt2800_bbp_write(rt2x00dev, 158, 0x29);
9960 rt2800_bbp_write(rt2x00dev, 159, bbp);
9962 rt2800_bbp_write(rt2x00dev, 158, 0x46);
9964 rt2800_bbp_write(rt2x00dev, 159, bbp);
9966 rt2800_bbp_write(rt2x00dev, 158, 0x47);
9968 rt2800_bbp_write(rt2x00dev, 159, bbp);
9970 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9971 rt2800_bbp_write(rt2x00dev, 1, bbpr1);
9972 rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9973 rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9975 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9977 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9978 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9979 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9980 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9982 rt2800_bbp_write(rt2x00dev, 30, bbpr30);
9983 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
9984 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9986 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9987 rt2800_bbp_write(rt2x00dev, 4, bbpr4);
9989 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9991 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9993 rt2800_rf_configrecover(rt2x00dev, rf_store);
9995 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9996 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9997 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9998 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
10000 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
10001 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
10002 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
10003 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
10004 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
10007 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
10012 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10014 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10018 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10020 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10024 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10026 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10030 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
10035 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
10037 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
10039 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
10041 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10043 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
10046 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
10047 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
10048 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10049 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10052 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10053 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10056 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10057 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
10059 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
10060 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
10061 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10062 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10065 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10066 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10069 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10075 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10081 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10086 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
10093 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
10101 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
10104 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10122 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
10123 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
10126 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
10128 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
10129 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10132 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10133 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10134 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10135 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10136 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
10137 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10138 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10139 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10140 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10141 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
10142 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
10143 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
10145 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
10146 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
10147 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
10148 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
10149 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
10150 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
10151 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
10152 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
10153 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
10154 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
10156 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10157 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10159 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10161 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10163 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10165 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
10170 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10176 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10179 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10182 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
10185 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
10205 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10210 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
10212 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
10214 rt2800_rf_lp_config(rt2x00dev, btxcal);
10217 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10219 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10220 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10222 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10225 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10227 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10228 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10230 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10235 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10237 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10239 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10241 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10243 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10245 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10248 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10251 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10252 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10255 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10257 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10260 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10261 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10264 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10269 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10271 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
10310 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
10311 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
10312 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
10313 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
10314 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
10315 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
10316 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
10317 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
10318 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
10319 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
10320 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
10322 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
10323 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
10324 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
10325 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
10326 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
10327 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
10328 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
10329 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
10330 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
10331 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
10333 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
10334 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
10336 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
10338 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
10339 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
10341 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10343 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10344 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10346 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
10347 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
10350 static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
10352 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10353 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
10354 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
10357 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10358 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10359 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10360 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10363 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10364 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3);
10365 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3);
10366 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5);
10367 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10368 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c);
10369 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc);
10370 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f);
10371 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10372 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10373 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff);
10374 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c);
10375 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10376 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b);
10377 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7);
10378 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10381 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10382 rt2800_bbp_write(rt2x00dev, 75, 0x60);
10383 rt2800_bbp_write(rt2x00dev, 76, 0x44);
10384 rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10385 rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10386 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
10389 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10390 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a);
10391 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c);
10392 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c);
10396 static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
10400 if (rt2x00_has_cap_external_pa(rt2x00dev) ||
10401 rt2x00_has_cap_external_lna_bg(rt2x00dev))
10402 rt2800_restore_rf_bbp_rt6352(rt2x00dev);
10404 rt2800_r_calibration(rt2x00dev);
10405 rt2800_rf_self_txdc_cal(rt2x00dev);
10406 rt2800_rxdcoc_calibration(rt2x00dev);
10407 rt2800_bw_filter_calibration(rt2x00dev, true);
10408 rt2800_bw_filter_calibration(rt2x00dev, false);
10409 rt2800_loft_iq_calibration(rt2x00dev);
10413 rt2800_rxdcoc_calibration(rt2x00dev);
10414 rt2800_rxiq_calibration(rt2x00dev);
10416 if (!rt2x00_has_cap_external_pa(rt2x00dev) &&
10417 !rt2x00_has_cap_external_lna_bg(rt2x00dev))
10420 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10421 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
10423 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
10425 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
10427 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
10430 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10431 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
10432 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
10433 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
10436 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10437 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
10438 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
10439 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
10440 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10441 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8);
10442 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4);
10443 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
10444 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10445 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8);
10446 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4);
10447 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
10448 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
10449 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8);
10450 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4);
10451 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
10454 if (rt2x00_has_cap_external_pa(rt2x00dev))
10455 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
10457 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10458 rt2800_bbp_write(rt2x00dev, 75, 0x68);
10459 rt2800_bbp_write(rt2x00dev, 76, 0x4c);
10460 rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10461 rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10462 rt2800_bbp_write(rt2x00dev, 82, 0xb6);
10465 if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10466 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
10467 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c);
10468 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c);
10472 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
10475 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
10476 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
10477 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
10478 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
10479 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
10480 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
10481 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
10482 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
10483 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
10484 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
10485 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
10486 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
10487 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10488 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10489 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
10490 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
10491 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
10492 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
10493 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
10494 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
10495 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
10496 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
10497 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
10498 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
10499 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
10500 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
10501 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
10502 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10503 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
10504 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
10505 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
10506 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
10507 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
10508 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
10509 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
10510 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
10511 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
10512 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
10513 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
10514 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
10515 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
10516 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
10517 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
10518 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
10520 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
10521 if (rt2800_clk_is_20mhz(rt2x00dev))
10522 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
10524 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10525 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
10526 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
10527 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
10528 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
10529 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
10530 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
10531 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
10532 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
10533 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
10534 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
10535 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
10536 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
10537 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10538 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
10539 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
10540 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
10542 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
10543 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
10544 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
10547 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
10548 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
10549 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
10550 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
10551 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
10552 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
10553 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
10554 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
10555 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
10556 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
10557 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
10558 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10559 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
10560 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
10561 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10562 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
10563 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
10564 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
10565 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10566 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10567 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
10568 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
10569 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
10570 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
10571 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
10572 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
10573 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
10574 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
10575 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
10576 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
10577 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
10578 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
10579 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
10580 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
10581 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
10582 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
10583 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
10584 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
10585 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
10586 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
10587 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
10588 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
10589 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
10590 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
10591 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
10592 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10593 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
10594 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
10595 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
10596 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
10597 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
10598 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
10599 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
10600 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
10601 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
10602 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
10603 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
10604 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
10605 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
10606 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
10608 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
10610 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
10611 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
10612 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
10613 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
10614 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10615 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
10616 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
10617 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
10618 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
10619 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
10620 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
10621 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
10622 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
10623 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
10624 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10625 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
10626 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10627 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10628 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
10629 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
10630 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
10631 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
10632 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
10633 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10634 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
10635 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
10636 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10637 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10638 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
10639 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10641 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
10642 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10643 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10644 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
10645 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
10646 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
10647 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
10648 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10649 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10651 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
10652 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
10653 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
10654 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10655 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10656 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10659 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10660 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
10661 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
10662 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
10663 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
10664 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
10665 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
10666 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
10669 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
10670 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
10671 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
10672 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
10673 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
10674 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10675 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
10676 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
10677 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
10678 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
10679 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
10680 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
10681 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
10682 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
10683 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
10684 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
10685 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
10686 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
10687 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
10688 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
10689 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
10690 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
10691 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
10692 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
10693 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
10694 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
10695 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
10696 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
10697 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
10698 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
10699 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
10700 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
10701 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
10702 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
10703 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
10704 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
10705 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
10706 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
10707 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
10708 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
10709 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
10710 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
10711 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
10712 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
10713 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
10714 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
10715 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
10716 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
10717 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
10718 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
10719 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
10720 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
10721 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
10722 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
10723 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
10724 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
10725 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
10726 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
10727 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
10729 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
10730 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
10731 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
10733 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10734 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
10737 rt2800_calibration_rt6352(rt2x00dev);
10740 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
10742 if (rt2800_is_305x_soc(rt2x00dev)) {
10743 rt2800_init_rfcsr_305x_soc(rt2x00dev);
10747 switch (rt2x00dev->chip.rt) {
10751 rt2800_init_rfcsr_30xx(rt2x00dev);
10754 rt2800_init_rfcsr_3290(rt2x00dev);
10757 rt2800_init_rfcsr_3352(rt2x00dev);
10760 rt2800_init_rfcsr_3390(rt2x00dev);
10763 rt2800_init_rfcsr_3883(rt2x00dev);
10766 rt2800_init_rfcsr_3572(rt2x00dev);
10769 rt2800_init_rfcsr_3593(rt2x00dev);
10772 rt2800_init_rfcsr_5350(rt2x00dev);
10775 rt2800_init_rfcsr_5390(rt2x00dev);
10778 rt2800_init_rfcsr_5392(rt2x00dev);
10781 rt2800_init_rfcsr_5592(rt2x00dev);
10784 rt2800_init_rfcsr_6352(rt2x00dev);
10789 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
10797 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
10798 rt2800_init_registers(rt2x00dev)))
10804 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
10810 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
10811 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
10812 if (rt2x00_is_usb(rt2x00dev))
10813 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
10814 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
10820 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
10826 rt2800_init_bbp(rt2x00dev);
10827 rt2800_init_rfcsr(rt2x00dev);
10829 if (rt2x00_is_usb(rt2x00dev) &&
10830 (rt2x00_rt(rt2x00dev, RT3070) ||
10831 rt2x00_rt(rt2x00dev, RT3071) ||
10832 rt2x00_rt(rt2x00dev, RT3572))) {
10834 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
10841 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10844 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10848 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
10852 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
10854 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10857 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10862 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
10863 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
10866 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
10867 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
10870 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
10871 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
10878 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
10882 rt2800_disable_wpdma(rt2x00dev);
10885 rt2800_wait_wpdma_ready(rt2x00dev);
10887 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10890 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10894 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
10899 if (rt2x00_rt(rt2x00dev, RT3290))
10904 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
10909 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
10918 if (rt2x00_rt(rt2x00dev, RT3290)) {
10931 mutex_lock(&rt2x00dev->csr_mutex);
10933 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
10937 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
10940 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
10942 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
10944 *(__le32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10945 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
10946 *(__le32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10947 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
10948 *(__le32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10949 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
10950 *(__le32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10952 mutex_unlock(&rt2x00dev->csr_mutex);
10955 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
10960 rt2800_efuse_read(rt2x00dev, i);
10966 int rt2800_read_eeprom_nvmem(struct rt2x00_dev *rt2x00dev)
10968 struct device *dev = rt2x00dev->dev;
10969 unsigned int len = rt2x00dev->ops->eeprom_size;
10985 dev_err(rt2x00dev->dev, "invalid eeprom size, required: 0x%04x\n", len);
10990 memcpy(rt2x00dev->eeprom, data, len);
10996 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
11000 if (rt2x00_rt(rt2x00dev, RT3593) ||
11001 rt2x00_rt(rt2x00dev, RT3883))
11004 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
11011 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
11015 if (rt2x00_rt(rt2x00dev, RT3593) ||
11016 rt2x00_rt(rt2x00dev, RT3883))
11019 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
11026 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
11028 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
11037 retval = rt2800_read_eeprom(rt2x00dev);
11044 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
11045 retval = rt2x00lib_set_mac_address(rt2x00dev, mac);
11049 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11054 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11055 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
11056 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
11057 rt2x00_rt(rt2x00dev, RT2872)) {
11063 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11066 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11083 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
11084 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
11087 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11090 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11091 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
11097 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11098 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
11099 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
11100 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
11101 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
11109 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
11112 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
11117 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
11119 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
11121 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
11124 if (!rt2x00_rt(rt2x00dev, RT3593) &&
11125 !rt2x00_rt(rt2x00dev, RT3883)) {
11131 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
11133 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
11135 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
11140 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
11142 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
11145 if (!rt2x00_rt(rt2x00dev, RT3593) &&
11146 !rt2x00_rt(rt2x00dev, RT3883)) {
11152 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
11154 if (rt2x00_rt(rt2x00dev, RT3593) ||
11155 rt2x00_rt(rt2x00dev, RT3883)) {
11156 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
11165 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
11171 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
11180 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11187 if (rt2x00_rt(rt2x00dev, RT3290) ||
11188 rt2x00_rt(rt2x00dev, RT5390) ||
11189 rt2x00_rt(rt2x00dev, RT5392) ||
11190 rt2x00_rt(rt2x00dev, RT6352))
11191 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
11192 else if (rt2x00_rt(rt2x00dev, RT3352))
11194 else if (rt2x00_rt(rt2x00dev, RT3883))
11196 else if (rt2x00_rt(rt2x00dev, RT5350))
11198 else if (rt2x00_rt(rt2x00dev, RT5592))
11230 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
11235 rt2x00_set_rf(rt2x00dev, rf);
11240 rt2x00dev->default_ant.tx_chain_num =
11242 rt2x00dev->default_ant.rx_chain_num =
11245 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11247 if (rt2x00_rt(rt2x00dev, RT3070) ||
11248 rt2x00_rt(rt2x00dev, RT3090) ||
11249 rt2x00_rt(rt2x00dev, RT3352) ||
11250 rt2x00_rt(rt2x00dev, RT3390)) {
11257 rt2x00dev->default_ant.tx = ANTENNA_A;
11258 rt2x00dev->default_ant.rx = ANTENNA_A;
11261 rt2x00dev->default_ant.tx = ANTENNA_A;
11262 rt2x00dev->default_ant.rx = ANTENNA_B;
11266 rt2x00dev->default_ant.tx = ANTENNA_A;
11267 rt2x00dev->default_ant.rx = ANTENNA_A;
11271 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
11272 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
11273 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11274 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11281 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11283 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11289 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11294 if (!rt2x00_rt(rt2x00dev, RT3352) &&
11296 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11301 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11302 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11308 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11309 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11310 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11312 rt2x00dev->led_mcu_reg = eeprom;
11318 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
11322 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11327 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11329 if (rt2x00_rt(rt2x00dev, RT3352) ||
11330 rt2x00_rt(rt2x00dev, RT6352)) {
11334 &rt2x00dev->cap_flags);
11338 &rt2x00dev->cap_flags);
11341 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
11343 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
11347 &rt2x00dev->cap_flags);
11349 &rt2x00dev->cap_flags);
11727 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
11729 struct hw_mode_spec *spec = &rt2x00dev->spec;
11740 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11746 rt2x00dev->hw->wiphy->retry_short = 2;
11747 rt2x00dev->hw->wiphy->retry_long = 2;
11752 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11753 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11754 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11755 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11756 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11765 if (!rt2x00_is_usb(rt2x00dev))
11766 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11768 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11770 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11771 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11772 rt2800_eeprom_addr(rt2x00dev,
11784 rt2x00dev->hw->max_rates = 1;
11785 rt2x00dev->hw->max_report_rates = 7;
11786 rt2x00dev->hw->max_rate_tries = 1;
11793 switch (rt2x00dev->chip.rf) {
11822 if (rt2800_clk_is_20mhz(rt2x00dev))
11845 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
11866 if (!rt2x00_rf(rt2x00dev, RF2020))
11877 tx_chains = rt2x00dev->default_ant.tx_chain_num;
11878 rx_chains = rt2x00dev->default_ant.rx_chain_num;
11914 rt2x00dev->chan_survey =
11916 if (!rt2x00dev->chan_survey) {
11923 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
11924 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
11926 if (rt2x00dev->default_ant.tx_chain_num > 2)
11927 default_power3 = rt2800_eeprom_addr(rt2x00dev,
11940 default_power1 = rt2800_eeprom_addr(rt2x00dev,
11942 default_power2 = rt2800_eeprom_addr(rt2x00dev,
11945 if (rt2x00dev->default_ant.tx_chain_num > 2)
11947 rt2800_eeprom_addr(rt2x00dev,
11960 switch (rt2x00dev->chip.rf) {
11980 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
11987 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
11993 if (rt2x00_rt(rt2x00dev, RT3290))
11994 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
11996 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
12020 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
12025 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
12028 rt2x00_set_rt(rt2x00dev, rt, rev);
12033 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
12038 retval = rt2800_probe_rt(rt2x00dev);
12045 retval = rt2800_validate_eeprom(rt2x00dev);
12049 retval = rt2800_init_eeprom(rt2x00dev);
12057 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
12059 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
12064 retval = rt2800_probe_hw_mode(rt2x00dev);
12071 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
12072 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
12073 if (!rt2x00_is_usb(rt2x00dev))
12074 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
12079 if (!rt2x00_is_soc(rt2x00dev))
12080 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
12081 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
12082 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
12083 if (!rt2800_hwcrypt_disabled(rt2x00dev))
12084 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
12085 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
12086 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
12087 if (rt2x00_is_usb(rt2x00dev))
12088 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
12090 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
12091 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
12094 rt2x00dev->link.watchdog = modparam_watchdog;
12096 if (rt2x00_is_usb(rt2x00dev))
12097 rt2x00dev->link.watchdog &= ~RT2800_WATCHDOG_DMA_BUSY;
12098 if (rt2x00dev->link.watchdog) {
12099 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
12100 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
12106 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
12119 struct rt2x00_dev *rt2x00dev = hw->priv;
12127 rt2800_register_multiread(rt2x00dev, offset,
12137 struct rt2x00_dev *rt2x00dev = hw->priv;
12141 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
12143 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
12145 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
12147 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
12149 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
12151 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
12153 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
12155 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
12157 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
12159 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
12161 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
12163 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
12165 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
12167 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
12178 struct rt2x00_dev *rt2x00dev = hw->priv;
12202 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
12209 reg = rt2800_register_read(rt2x00dev, offset);
12211 rt2800_register_write(rt2x00dev, offset, reg);
12217 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
12219 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
12221 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
12223 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
12225 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
12227 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
12232 reg = rt2800_register_read(rt2x00dev, offset);
12237 rt2800_register_write(rt2x00dev, offset, reg);
12245 struct rt2x00_dev *rt2x00dev = hw->priv;
12249 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
12251 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
12309 struct rt2x00_dev *rt2x00dev = hw->priv;
12311 &rt2x00dev->chan_survey[idx];
12314 if (idx >= rt2x00dev->bands[band].n_channels) {
12315 idx -= rt2x00dev->bands[band].n_channels;
12319 if (idx >= rt2x00dev->bands[band].n_channels)
12323 rt2800_update_survey(rt2x00dev);
12325 survey->channel = &rt2x00dev->bands[band].channels[idx];