Lines Matching refs:ci
241 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
246 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
252 struct brcmf_chip_priv *ci;
256 ci = core->chip;
258 regdata = ci->ops->read32(ci->ctx, address);
266 struct brcmf_chip_priv *ci;
270 ci = core->chip;
271 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
274 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
283 struct brcmf_chip_priv *ci;
286 ci = core->chip;
288 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
292 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
298 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
299 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
302 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
304 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
307 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
311 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
313 val = ci->ops->read32(ci->ctx,
316 ci->ops->write32(ci->ctx,
318 val = ci->ops->read32(ci->ctx,
321 SPINWAIT((ci->ops->read32(ci->ctx,
329 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
330 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
334 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
336 val = ci->ops->read32(ci->ctx,
339 ci->ops->write32(ci->ctx,
345 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
353 struct brcmf_chip_priv *ci;
356 ci = core->chip;
359 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
364 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
366 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
369 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
374 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
379 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
381 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
387 struct brcmf_chip_priv *ci;
391 ci = core->chip;
404 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
407 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
411 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
413 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
415 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
418 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
422 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
424 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
428 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
430 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
437 struct brcmf_chip_priv *ci;
442 ci = core->chip;
446 d11core2 = brcmf_chip_get_d11core(&ci->pub, 1);
460 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
462 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
471 while (ci->ops->read32(ci->ctx,
474 ci->ops->write32(ci->ctx,
484 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
486 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
489 ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL,
491 ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
504 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
516 core->chip = ci;
519 list_add_tail(&core->list, &ci->cores);
524 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
532 list_for_each_entry(core, &ci->cores, list) {
710 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
712 switch (ci->pub.chip) {
737 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000;
750 brcmf_err("unknown chip: %s\n", ci->pub.name);
758 struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
763 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
766 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
767 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
768 if (ci->pub.rambase == INVALID_RAMBASE) {
773 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
777 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
778 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
779 if (ci->pub.rambase == INVALID_RAMBASE) {
784 mem = brcmf_chip_get_core(&ci->pub,
792 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
793 &ci->pub.srsize);
797 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
798 ci->pub.srsize, ci->pub.srsize);
800 if (!ci->pub.ramsize) {
805 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
813 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
819 val = ci->ops->read32(ci->ctx, *eromaddr);
833 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
843 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
858 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
875 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
881 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
884 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
905 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
916 eromaddr = ci->ops->read32(ci->ctx,
917 CORE_CC_REG(ci->pub.enum_base, eromptr));
920 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
934 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
950 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
955 core = brcmf_chip_add_core(ci, id, base, wrap);
970 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
983 regdata = ci->ops->read32(ci->ctx,
984 CORE_CC_REG(ci->pub.enum_base, chipid));
990 ci->pub.chip = regdata & CID_ID_MASK;
991 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
994 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
995 ci->pub.name, sizeof(ci->pub.name));
997 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
1000 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
1004 ci->iscoreup = brcmf_chip_sb_iscoreup;
1005 ci->coredisable = brcmf_chip_sb_coredisable;
1006 ci->resetcore = brcmf_chip_sb_resetcore;
1008 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
1010 brcmf_chip_sb_corerev(ci, core);
1011 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
1013 brcmf_chip_sb_corerev(ci, core);
1014 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
1016 brcmf_chip_sb_corerev(ci, core);
1017 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
1019 brcmf_chip_sb_corerev(ci, core);
1021 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
1022 brcmf_chip_sb_corerev(ci, core);
1024 ci->iscoreup = brcmf_chip_ai_iscoreup;
1025 ci->coredisable = brcmf_chip_ai_coredisable;
1026 ci->resetcore = brcmf_chip_ai_resetcore;
1028 brcmf_chip_dmp_erom_scan(ci);
1035 ret = brcmf_chip_cores_check(ci);
1040 brcmf_chip_set_passive(&ci->pub);
1045 if (ci->ops->reset) {
1046 ci->ops->reset(ci->ctx, &ci->pub);
1047 brcmf_chip_set_passive(&ci->pub);
1050 return brcmf_chip_get_raminfo(&ci->pub);