Lines Matching refs:dev
54 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
68 static void generate_rfatt_list(struct b43_wldev *dev,
71 struct b43_phy *phy = &dev->phy;
111 if (!b43_has_hardware_pctl(dev)) {
134 static void generate_bbatt_list(struct b43_wldev *dev,
155 static void b43_shm_clear_tssi(struct b43_wldev *dev)
157 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
158 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
159 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
160 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
164 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
166 struct b43_phy *phy = &dev->phy;
176 b43_write16(dev, B43_MMIO_CHANNEL,
179 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
182 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
186 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
189 struct b43_phy *phy = &dev->phy;
192 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
196 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
198 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
203 static void b43_set_txpower_g(struct b43_wldev *dev,
207 struct b43_phy *phy = &dev->phy;
227 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
228 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
234 b43_gphy_set_baseband_attenuation(dev, bb);
235 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
237 b43_radio_write16(dev, 0x43,
240 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F));
241 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070));
244 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
246 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F));
248 b43_lo_g_adjust(dev);
252 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
254 struct b43_phy_g *gphy = dev->phy.g;
259 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
261 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
265 b43_phy_write(dev, 0x380 + (i / 2), value);
270 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
272 struct b43_phy *phy = &dev->phy;
290 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
296 static void b43_set_all_gains(struct b43_wldev *dev,
299 struct b43_phy *phy = &dev->phy;
314 b43_ofdmtab_write16(dev, table, i, first);
317 b43_ofdmtab_write16(dev, table, i, second);
321 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
322 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
323 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
325 b43_dummy_transmission(dev, false, true);
328 static void b43_set_original_gains(struct b43_wldev *dev)
330 struct b43_phy *phy = &dev->phy;
348 b43_ofdmtab_write16(dev, table, i, tmp);
352 b43_ofdmtab_write16(dev, table, i, i - start);
354 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
355 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
356 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
357 b43_dummy_transmission(dev, false, true);
361 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
363 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
364 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
368 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
372 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
373 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
379 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
385 tmp = b43_nrssi_hw_read(dev, i);
388 b43_nrssi_hw_write(dev, i, tmp);
393 static void b43_nrssi_mem_update(struct b43_wldev *dev)
395 struct b43_phy_g *gphy = dev->phy.g;
409 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
411 struct b43_phy *phy = &dev->phy;
417 backup[0] = b43_phy_read(dev, 0x0001);
418 backup[1] = b43_phy_read(dev, 0x0811);
419 backup[2] = b43_phy_read(dev, 0x0812);
421 backup[3] = b43_phy_read(dev, 0x0814);
422 backup[4] = b43_phy_read(dev, 0x0815);
424 backup[5] = b43_phy_read(dev, 0x005A);
425 backup[6] = b43_phy_read(dev, 0x0059);
426 backup[7] = b43_phy_read(dev, 0x0058);
427 backup[8] = b43_phy_read(dev, 0x000A);
428 backup[9] = b43_phy_read(dev, 0x0003);
429 backup[10] = b43_radio_read16(dev, 0x007A);
430 backup[11] = b43_radio_read16(dev, 0x0043);
432 b43_phy_mask(dev, 0x0429, 0x7FFF);
433 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
434 b43_phy_set(dev, 0x0811, 0x000C);
435 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
436 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
438 backup[12] = b43_phy_read(dev, 0x002E);
439 backup[13] = b43_phy_read(dev, 0x002F);
440 backup[14] = b43_phy_read(dev, 0x080F);
441 backup[15] = b43_phy_read(dev, 0x0810);
442 backup[16] = b43_phy_read(dev, 0x0801);
443 backup[17] = b43_phy_read(dev, 0x0060);
444 backup[18] = b43_phy_read(dev, 0x0014);
445 backup[19] = b43_phy_read(dev, 0x0478);
447 b43_phy_write(dev, 0x002E, 0);
448 b43_phy_write(dev, 0x002F, 0);
449 b43_phy_write(dev, 0x080F, 0);
450 b43_phy_write(dev, 0x0810, 0);
451 b43_phy_set(dev, 0x0478, 0x0100);
452 b43_phy_set(dev, 0x0801, 0x0040);
453 b43_phy_set(dev, 0x0060, 0x0040);
454 b43_phy_set(dev, 0x0014, 0x0200);
456 b43_radio_set(dev, 0x007A, 0x0070);
457 b43_radio_set(dev, 0x007A, 0x0080);
460 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
465 b43_radio_write16(dev, 0x007B, i);
468 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
477 b43_radio_mask(dev, 0x007A, 0x007F);
479 b43_phy_set(dev, 0x0814, 0x0001);
480 b43_phy_mask(dev, 0x0815, 0xFFFE);
482 b43_phy_set(dev, 0x0811, 0x000C);
483 b43_phy_set(dev, 0x0812, 0x000C);
484 b43_phy_set(dev, 0x0811, 0x0030);
485 b43_phy_set(dev, 0x0812, 0x0030);
486 b43_phy_write(dev, 0x005A, 0x0480);
487 b43_phy_write(dev, 0x0059, 0x0810);
488 b43_phy_write(dev, 0x0058, 0x000D);
490 b43_phy_write(dev, 0x0003, 0x0122);
492 b43_phy_set(dev, 0x000A, 0x2000);
495 b43_phy_set(dev, 0x0814, 0x0004);
496 b43_phy_mask(dev, 0x0815, 0xFFFB);
498 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
499 b43_radio_set(dev, 0x007A, 0x000F);
500 b43_set_all_gains(dev, 3, 0, 1);
501 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F);
503 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
508 b43_radio_write16(dev, 0x007B, i);
511 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
523 b43_radio_write16(dev, 0x007B, saved);
526 b43_phy_write(dev, 0x002E, backup[12]);
527 b43_phy_write(dev, 0x002F, backup[13]);
528 b43_phy_write(dev, 0x080F, backup[14]);
529 b43_phy_write(dev, 0x0810, backup[15]);
532 b43_phy_write(dev, 0x0814, backup[3]);
533 b43_phy_write(dev, 0x0815, backup[4]);
535 b43_phy_write(dev, 0x005A, backup[5]);
536 b43_phy_write(dev, 0x0059, backup[6]);
537 b43_phy_write(dev, 0x0058, backup[7]);
538 b43_phy_write(dev, 0x000A, backup[8]);
539 b43_phy_write(dev, 0x0003, backup[9]);
540 b43_radio_write16(dev, 0x0043, backup[11]);
541 b43_radio_write16(dev, 0x007A, backup[10]);
542 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
543 b43_phy_set(dev, 0x0429, 0x8000);
544 b43_set_original_gains(dev);
546 b43_phy_write(dev, 0x0801, backup[16]);
547 b43_phy_write(dev, 0x0060, backup[17]);
548 b43_phy_write(dev, 0x0014, backup[18]);
549 b43_phy_write(dev, 0x0478, backup[19]);
551 b43_phy_write(dev, 0x0001, backup[0]);
552 b43_phy_write(dev, 0x0812, backup[2]);
553 b43_phy_write(dev, 0x0811, backup[1]);
556 static void b43_calc_nrssi_slope(struct b43_wldev *dev)
558 struct b43_phy *phy = &dev->phy;
569 b43_calc_nrssi_offset(dev);
571 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
572 b43_phy_mask(dev, 0x0802, 0xFFFC);
573 backup[7] = b43_read16(dev, 0x03E2);
574 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
575 backup[0] = b43_radio_read16(dev, 0x007A);
576 backup[1] = b43_radio_read16(dev, 0x0052);
577 backup[2] = b43_radio_read16(dev, 0x0043);
578 backup[3] = b43_phy_read(dev, 0x0015);
579 backup[4] = b43_phy_read(dev, 0x005A);
580 backup[5] = b43_phy_read(dev, 0x0059);
581 backup[6] = b43_phy_read(dev, 0x0058);
582 backup[8] = b43_read16(dev, 0x03E6);
583 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
585 backup[10] = b43_phy_read(dev, 0x002E);
586 backup[11] = b43_phy_read(dev, 0x002F);
587 backup[12] = b43_phy_read(dev, 0x080F);
588 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
589 backup[14] = b43_phy_read(dev, 0x0801);
590 backup[15] = b43_phy_read(dev, 0x0060);
591 backup[16] = b43_phy_read(dev, 0x0014);
592 backup[17] = b43_phy_read(dev, 0x0478);
593 b43_phy_write(dev, 0x002E, 0);
594 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
599 b43_phy_set(dev, 0x0478, 0x0100);
600 b43_phy_set(dev, 0x0801, 0x0040);
604 b43_phy_mask(dev, 0x0801, 0xFFBF);
607 b43_phy_set(dev, 0x0060, 0x0040);
608 b43_phy_set(dev, 0x0014, 0x0200);
610 b43_radio_set(dev, 0x007A, 0x0070);
611 b43_set_all_gains(dev, 0, 8, 0);
612 b43_radio_mask(dev, 0x007A, 0x00F7);
614 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
615 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
617 b43_radio_set(dev, 0x007A, 0x0080);
620 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
624 b43_radio_mask(dev, 0x007A, 0x007F);
626 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
629 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
630 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
632 b43_radio_set(dev, 0x007A, 0x000F);
633 b43_phy_write(dev, 0x0015, 0xF330);
635 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
636 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
639 b43_set_all_gains(dev, 3, 0, 1);
641 b43_radio_write16(dev, 0x0043, 0x001F);
643 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
644 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
645 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
646 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
648 b43_phy_write(dev, 0x005A, 0x0480);
649 b43_phy_write(dev, 0x0059, 0x0810);
650 b43_phy_write(dev, 0x0058, 0x000D);
652 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
664 b43_phy_write(dev, 0x002E, backup[10]);
665 b43_phy_write(dev, 0x002F, backup[11]);
666 b43_phy_write(dev, 0x080F, backup[12]);
667 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
670 b43_phy_mask(dev, 0x0812, 0xFFCF);
671 b43_phy_mask(dev, 0x0811, 0xFFCF);
674 b43_radio_write16(dev, 0x007A, backup[0]);
675 b43_radio_write16(dev, 0x0052, backup[1]);
676 b43_radio_write16(dev, 0x0043, backup[2]);
677 b43_write16(dev, 0x03E2, backup[7]);
678 b43_write16(dev, 0x03E6, backup[8]);
679 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
680 b43_phy_write(dev, 0x0015, backup[3]);
681 b43_phy_write(dev, 0x005A, backup[4]);
682 b43_phy_write(dev, 0x0059, backup[5]);
683 b43_phy_write(dev, 0x0058, backup[6]);
684 b43_synth_pu_workaround(dev, phy->channel);
685 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
686 b43_set_original_gains(dev);
687 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
689 b43_phy_write(dev, 0x0801, backup[14]);
690 b43_phy_write(dev, 0x0060, backup[15]);
691 b43_phy_write(dev, 0x0014, backup[16]);
692 b43_phy_write(dev, 0x0478, backup[17]);
694 b43_nrssi_mem_update(dev);
695 b43_calc_nrssi_threshold(dev);
698 static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
700 struct b43_phy *phy = &dev->phy;
709 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
710 tmp16 = b43_nrssi_hw_read(dev, 0x20);
714 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
716 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
748 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
751 b43_phy_write(dev, 0x048A, tmp_u16);
794 b43_phy_read(dev, (offset))); \
798 b43_phy_write(dev, (offset), \
805 b43_radio_read16(dev, (offset))); \
809 b43_radio_write16(dev, (offset), \
816 b43_ofdmtab_read16(dev, (table), (offset))); \
820 b43_ofdmtab_write16(dev, (table), (offset), \
826 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
828 struct b43_phy *phy = &dev->phy;
837 b43_phy_set(dev, 0x042B, 0x0800);
838 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
842 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
850 b43_radio_write16(dev, 0x0078, flipped);
852 b43_calc_nrssi_threshold(dev);
855 b43_phy_write(dev, 0x0406, 0x7E28);
857 b43_phy_set(dev, 0x042B, 0x0800);
858 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
861 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
863 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
865 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
867 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
869 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
872 b43_phy_write(dev, 0x04A7, 0x0002);
874 b43_phy_write(dev, 0x04A3, 0x287A);
876 b43_phy_write(dev, 0x04A9, 0x2027);
878 b43_phy_write(dev, 0x0493, 0x32F5);
880 b43_phy_write(dev, 0x04AA, 0x2027);
882 b43_phy_write(dev, 0x04AC, 0x32F5);
885 if (b43_phy_read(dev, 0x0033) & 0x0800)
925 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
926 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
928 b43_phy_write(dev, 0x0033, 0x0800);
929 b43_phy_write(dev, 0x04A3, 0x2027);
930 b43_phy_write(dev, 0x04A9, 0x1CA8);
931 b43_phy_write(dev, 0x0493, 0x287A);
932 b43_phy_write(dev, 0x04AA, 0x1CA8);
933 b43_phy_write(dev, 0x04AC, 0x287A);
935 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
936 b43_phy_write(dev, 0x04A7, 0x000D);
939 b43_phy_write(dev, 0x0406, 0xFF0D);
941 b43_phy_write(dev, 0x04C0, 0xFFFF);
942 b43_phy_write(dev, 0x04C1, 0x00A9);
944 b43_phy_write(dev, 0x04C0, 0x00C1);
945 b43_phy_write(dev, 0x04C1, 0x0059);
948 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
949 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
950 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
951 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
952 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
953 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
954 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
955 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
956 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
957 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
958 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
959 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
960 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
963 b43_phy_mask(dev, 0x048A, 0x7FFF);
964 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
965 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
966 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
968 b43_phy_set(dev, 0x048A, 0x1000);
969 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
970 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
973 b43_phy_set(dev, 0x042B, 0x0800);
975 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
977 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
978 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
980 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
981 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
982 b43_phy_mask(dev, 0x04AD, 0x00FF);
984 b43_calc_nrssi_slope(dev);
992 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
994 struct b43_phy *phy = &dev->phy;
1001 b43_phy_mask(dev, 0x042B, ~0x0800);
1002 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1006 b43_calc_nrssi_threshold(dev);
1008 b43_phy_mask(dev, 0x042B, ~0x0800);
1009 if (!dev->bad_frames_preempt) {
1010 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1012 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1026 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1064 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1065 b43_calc_nrssi_slope(dev);
1079 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1090 reg = b43_radio_read16(dev, 0x60);
1100 static u16 radio2050_rfover_val(struct b43_wldev *dev,
1103 struct b43_phy *phy = &dev->phy;
1105 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1245 static u16 b43_radio_init2050(struct b43_wldev *dev)
1247 struct b43_phy *phy = &dev->phy;
1257 sav.radio_43 = b43_radio_read16(dev, 0x43);
1258 sav.radio_51 = b43_radio_read16(dev, 0x51);
1259 sav.radio_52 = b43_radio_read16(dev, 0x52);
1260 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1261 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1262 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1263 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1266 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1267 sav.reg_3EC = b43_read16(dev, 0x3EC);
1269 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1270 b43_write16(dev, 0x3EC, 0x3F3F);
1272 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1273 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1274 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1276 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1277 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1278 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1280 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1281 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1282 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1283 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1285 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1286 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1289 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1291 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1292 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1295 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1296 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1298 b43_phy_write(dev, B43_PHY_RFOVER,
1299 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1301 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1303 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1304 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1305 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1306 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1309 b43_write16(dev, 0x03E6, 0x0122);
1312 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1314 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1315 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1318 rcc = b43_radio_core_calibration_value(dev);
1321 b43_radio_write16(dev, 0x78, 0x26);
1323 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1324 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1327 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1328 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1330 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1331 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1334 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1335 b43_radio_set(dev, 0x51, 0x0004);
1337 b43_radio_write16(dev, 0x43, 0x1F);
1339 b43_radio_write16(dev, 0x52, 0);
1340 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009);
1342 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1345 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1346 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1347 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1349 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1350 radio2050_rfover_val(dev,
1354 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1357 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1358 radio2050_rfover_val(dev,
1362 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1365 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1366 radio2050_rfover_val(dev,
1370 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1372 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1373 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1375 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1376 radio2050_rfover_val(dev,
1380 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1384 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1390 b43_radio_write16(dev, 0x78, radio78);
1393 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1394 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1395 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1397 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1398 radio2050_rfover_val(dev,
1403 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1406 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1407 radio2050_rfover_val(dev,
1412 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1415 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1416 radio2050_rfover_val(dev,
1421 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1423 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1424 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1426 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1427 radio2050_rfover_val(dev,
1432 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1441 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1442 b43_radio_write16(dev, 0x51, sav.radio_51);
1443 b43_radio_write16(dev, 0x52, sav.radio_52);
1444 b43_radio_write16(dev, 0x43, sav.radio_43);
1445 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1446 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1447 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1448 b43_write16(dev, 0x3E6, sav.reg_3E6);
1450 b43_write16(dev, 0x3F4, sav.reg_3F4);
1451 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1452 b43_synth_pu_workaround(dev, phy->channel);
1454 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1455 b43_write16(dev, 0x3EC, sav.reg_3EC);
1457 b43_write16(dev, B43_MMIO_PHY_RADIO,
1458 b43_read16(dev, B43_MMIO_PHY_RADIO)
1460 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1461 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1462 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1463 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1465 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1466 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1468 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1469 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1480 static void b43_phy_initb5(struct b43_wldev *dev)
1482 struct b43_phy *phy = &dev->phy;
1488 b43_radio_set(dev, 0x007A, 0x0050);
1490 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) &&
1491 (dev->dev->board_type != SSB_BOARD_BU4306)) {
1494 b43_phy_write(dev, offset, value);
1498 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1500 b43_phy_write(dev, 0x0038, 0x0667);
1504 b43_radio_set(dev, 0x007A, 0x0020);
1505 b43_radio_set(dev, 0x0051, 0x0004);
1507 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1509 b43_phy_set(dev, 0x0802, 0x0100);
1510 b43_phy_set(dev, 0x042B, 0x2000);
1512 b43_phy_write(dev, 0x001C, 0x186A);
1514 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1515 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1516 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1519 if (dev->bad_frames_preempt) {
1520 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1524 b43_phy_write(dev, 0x0026, 0xCE00);
1525 b43_phy_write(dev, 0x0021, 0x3763);
1526 b43_phy_write(dev, 0x0022, 0x1BC3);
1527 b43_phy_write(dev, 0x0023, 0x06F9);
1528 b43_phy_write(dev, 0x0024, 0x037E);
1530 b43_phy_write(dev, 0x0026, 0xCC00);
1531 b43_phy_write(dev, 0x0030, 0x00C6);
1532 b43_write16(dev, 0x03EC, 0x3F22);
1535 b43_phy_write(dev, 0x0020, 0x3E1C);
1537 b43_phy_write(dev, 0x0020, 0x301C);
1540 b43_write16(dev, 0x03E4, 0x3000);
1544 b43_gphy_channel_switch(dev, 7, 0);
1547 b43_radio_write16(dev, 0x0075, 0x0080);
1548 b43_radio_write16(dev, 0x0079, 0x0081);
1551 b43_radio_write16(dev, 0x0050, 0x0020);
1552 b43_radio_write16(dev, 0x0050, 0x0023);
1555 b43_radio_write16(dev, 0x0050, 0x0020);
1556 b43_radio_write16(dev, 0x005A, 0x0070);
1559 b43_radio_write16(dev, 0x005B, 0x007B);
1560 b43_radio_write16(dev, 0x005C, 0x00B0);
1562 b43_radio_set(dev, 0x007A, 0x0007);
1564 b43_gphy_channel_switch(dev, old_channel, 0);
1566 b43_phy_write(dev, 0x0014, 0x0080);
1567 b43_phy_write(dev, 0x0032, 0x00CA);
1568 b43_phy_write(dev, 0x002A, 0x88A3);
1570 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1573 b43_radio_write16(dev, 0x005D, 0x000D);
1575 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1579 static void b43_phy_initb6(struct b43_wldev *dev)
1581 struct b43_phy *phy = &dev->phy;
1586 b43_phy_write(dev, 0x003E, 0x817A);
1587 b43_radio_write16(dev, 0x007A,
1588 (b43_radio_read16(dev, 0x007A) | 0x0058));
1590 b43_radio_write16(dev, 0x51, 0x37);
1591 b43_radio_write16(dev, 0x52, 0x70);
1592 b43_radio_write16(dev, 0x53, 0xB3);
1593 b43_radio_write16(dev, 0x54, 0x9B);
1594 b43_radio_write16(dev, 0x5A, 0x88);
1595 b43_radio_write16(dev, 0x5B, 0x88);
1596 b43_radio_write16(dev, 0x5D, 0x88);
1597 b43_radio_write16(dev, 0x5E, 0x88);
1598 b43_radio_write16(dev, 0x7D, 0x88);
1599 b43_hf_write(dev, b43_hf_read(dev)
1604 b43_radio_write16(dev, 0x51, 0);
1605 b43_radio_write16(dev, 0x52, 0x40);
1606 b43_radio_write16(dev, 0x53, 0xB7);
1607 b43_radio_write16(dev, 0x54, 0x98);
1608 b43_radio_write16(dev, 0x5A, 0x88);
1609 b43_radio_write16(dev, 0x5B, 0x6B);
1610 b43_radio_write16(dev, 0x5C, 0x0F);
1611 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) {
1612 b43_radio_write16(dev, 0x5D, 0xFA);
1613 b43_radio_write16(dev, 0x5E, 0xD8);
1615 b43_radio_write16(dev, 0x5D, 0xF5);
1616 b43_radio_write16(dev, 0x5E, 0xB8);
1618 b43_radio_write16(dev, 0x0073, 0x0003);
1619 b43_radio_write16(dev, 0x007D, 0x00A8);
1620 b43_radio_write16(dev, 0x007C, 0x0001);
1621 b43_radio_write16(dev, 0x007E, 0x0008);
1625 b43_phy_write(dev, offset, val);
1630 b43_phy_write(dev, offset, val);
1635 b43_phy_write(dev, offset, (val & 0x3F3F));
1639 b43_radio_set(dev, 0x007A, 0x0020);
1640 b43_radio_set(dev, 0x0051, 0x0004);
1641 b43_phy_set(dev, 0x0802, 0x0100);
1642 b43_phy_set(dev, 0x042B, 0x2000);
1643 b43_phy_write(dev, 0x5B, 0);
1644 b43_phy_write(dev, 0x5C, 0);
1649 b43_gphy_channel_switch(dev, 1, 0);
1651 b43_gphy_channel_switch(dev, 13, 0);
1653 b43_radio_write16(dev, 0x0050, 0x0020);
1654 b43_radio_write16(dev, 0x0050, 0x0023);
1657 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1659 b43_radio_write16(dev, 0x50, 0x20);
1662 b43_radio_write16(dev, 0x50, 0x20);
1663 b43_radio_write16(dev, 0x5A, 0x70);
1664 b43_radio_write16(dev, 0x5B, 0x7B);
1665 b43_radio_write16(dev, 0x5C, 0xB0);
1667 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007);
1669 b43_gphy_channel_switch(dev, old_channel, 0);
1671 b43_phy_write(dev, 0x0014, 0x0200);
1673 b43_phy_write(dev, 0x2A, 0x88C2);
1675 b43_phy_write(dev, 0x2A, 0x8AC0);
1676 b43_phy_write(dev, 0x0038, 0x0668);
1677 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1679 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1681 b43_radio_write16(dev, 0x005D, 0x000D);
1684 b43_write16(dev, 0x3E4, 9);
1685 b43_phy_mask(dev, 0x61, 0x0FFF);
1687 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1692 b43_write16(dev, 0x03E6, 0x0);
1695 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1697 struct b43_phy *phy = &dev->phy;
1706 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1707 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1708 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1709 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1711 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1712 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1714 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1715 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1716 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1717 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1718 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1719 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1720 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1721 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1722 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1723 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1725 backup_radio[0] = b43_radio_read16(dev, 0x52);
1726 backup_radio[1] = b43_radio_read16(dev, 0x43);
1727 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1729 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1730 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1731 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1732 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1733 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1734 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1736 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1737 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1738 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1739 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1741 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1742 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1743 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1744 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1746 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1747 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1748 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1750 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1752 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1753 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1755 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1758 b43_radio_write16(dev, 0x43, 0x000F);
1760 b43_radio_write16(dev, 0x52, 0);
1761 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9);
1763 b43_gphy_set_baseband_attenuation(dev, 11);
1766 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1768 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1769 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1771 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1772 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1774 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1775 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1777 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) {
1779 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1780 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1783 b43_radio_mask(dev, 0x7A, 0x00F7);
1789 b43_radio_write16(dev, 0x43, i);
1790 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1791 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1792 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1794 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1802 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1805 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1806 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1807 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1810 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1818 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1819 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1821 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1822 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1823 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1824 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1825 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1826 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1827 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1828 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1829 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1831 b43_gphy_set_baseband_attenuation(dev, backup_bband);
1833 b43_radio_write16(dev, 0x52, backup_radio[0]);
1834 b43_radio_write16(dev, 0x43, backup_radio[1]);
1835 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1837 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1839 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1840 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1841 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1842 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1849 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1851 struct b43_phy *phy = &dev->phy;
1853 if (!b43_has_hardware_pctl(dev)) {
1854 b43_phy_write(dev, 0x047A, 0xC111);
1858 b43_phy_mask(dev, 0x0036, 0xFEFF);
1859 b43_phy_write(dev, 0x002F, 0x0202);
1860 b43_phy_set(dev, 0x047C, 0x0002);
1861 b43_phy_set(dev, 0x047A, 0xF000);
1863 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1864 b43_phy_set(dev, 0x005D, 0x8000);
1865 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1866 b43_phy_write(dev, 0x002E, 0xC07F);
1867 b43_phy_set(dev, 0x0036, 0x0400);
1869 b43_phy_set(dev, 0x0036, 0x0200);
1870 b43_phy_set(dev, 0x0036, 0x0400);
1871 b43_phy_mask(dev, 0x005D, 0x7FFF);
1872 b43_phy_mask(dev, 0x004F, 0xFFFE);
1873 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1874 b43_phy_write(dev, 0x002E, 0xC07F);
1875 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1880 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1882 struct b43_phy *phy = &dev->phy;
1885 if (!b43_has_hardware_pctl(dev)) {
1887 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
1891 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1892 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1893 b43_gphy_tssi_power_lt_init(dev);
1894 b43_gphy_gain_lt_init(dev);
1895 b43_phy_mask(dev, 0x0060, 0xFFBF);
1896 b43_phy_write(dev, 0x0014, 0x0000);
1899 b43_phy_set(dev, 0x0478, 0x0800);
1900 b43_phy_mask(dev, 0x0478, 0xFEFF);
1901 b43_phy_mask(dev, 0x0801, 0xFFBF);
1903 b43_gphy_dc_lt_init(dev, 1);
1906 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
1910 static void b43_phy_init_pctl(struct b43_wldev *dev)
1912 struct b43_phy *phy = &dev->phy;
1920 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
1921 (dev->dev->board_type == SSB_BOARD_BU4306))
1924 b43_phy_write(dev, 0x0028, 0x8018);
1927 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
1932 b43_hardware_pctl_early_init(dev);
1935 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084);
1952 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
1954 b43_dummy_transmission(dev, false, true);
1955 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
1959 b43dbg(dev->wl,
1968 b43_radio_mask(dev, 0x0076, 0xFF7B);
1970 b43_set_txpower_g(dev, &old_bbatt,
1974 b43_hardware_pctl_init_gphy(dev);
1975 b43_shm_clear_tssi(dev);
1978 static void b43_phy_inita(struct b43_wldev *dev)
1980 struct b43_phy *phy = &dev->phy;
1985 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
1986 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
1988 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
1991 b43_wa_all(dev);
1993 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
1994 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
1997 static void b43_phy_initg(struct b43_wldev *dev)
1999 struct b43_phy *phy = &dev->phy;
2004 b43_phy_initb5(dev);
2006 b43_phy_initb6(dev);
2009 b43_phy_inita(dev);
2012 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2013 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2016 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2017 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2020 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2021 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2024 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2027 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2028 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2031 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2035 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2037 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2038 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2041 b43_calc_loopback_gain(dev);
2045 gphy->initval = b43_radio_init2050(dev);
2047 b43_radio_write16(dev, 0x0078, gphy->initval);
2049 b43_lo_g_init(dev);
2051 b43_radio_write16(dev, 0x52,
2052 (b43_radio_read16(dev, 0x52) & 0xFF00)
2056 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias);
2059 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2061 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2062 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2064 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2066 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2068 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2070 b43_lo_g_adjust(dev);
2071 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2074 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
2081 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
2082 b43_calc_nrssi_threshold(dev);
2086 b43_calc_nrssi_slope(dev);
2088 b43_calc_nrssi_threshold(dev);
2091 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2092 b43_phy_init_pctl(dev);
2096 if ((dev->dev->chip_id == 0x4306
2097 && dev->dev->chip_pkg == 2) || 0) {
2098 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2099 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2103 void b43_gphy_channel_switch(struct b43_wldev *dev,
2108 b43_synth_pu_workaround(dev, channel);
2110 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2113 if (dev->dev->bus_sprom->country_code ==
2115 b43_hf_write(dev,
2116 b43_hf_read(dev) & ~B43_HF_ACPR);
2118 b43_hf_write(dev,
2119 b43_hf_read(dev) | B43_HF_ACPR);
2120 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2121 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2124 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2125 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2130 static void default_baseband_attenuation(struct b43_wldev *dev,
2133 struct b43_phy *phy = &dev->phy;
2141 static void default_radio_attenuation(struct b43_wldev *dev,
2144 struct b43_bus_dev *bdev = dev->dev;
2145 struct b43_phy *phy = &dev->phy;
2149 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM &&
2150 dev->dev->board_type == SSB_BOARD_BCM4309G) {
2151 if (dev->dev->board_rev < 0x43) {
2154 } else if (dev->dev->board_rev < 0x51) {
2237 static u16 default_tx_control(struct b43_wldev *dev)
2239 struct b43_phy *phy = &dev->phy;
2252 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2254 struct b43_phy *phy = &dev->phy;
2260 saved = b43_phy_read(dev, 0x0403);
2261 b43_switch_channel(dev, channel);
2262 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2264 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2271 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2279 b43_phy_write(dev, 0x0403, saved);
2284 static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2286 struct b43_phy *phy = &dev->phy;
2294 b43_phy_lock(dev);
2295 b43_radio_lock(dev);
2296 b43_phy_mask(dev, 0x0802, 0xFFFC);
2297 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2298 b43_set_all_gains(dev, 3, 8, 1);
2305 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2307 b43_switch_channel(dev, channel);
2308 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2309 b43_phy_mask(dev, 0x0403, 0xFFF8);
2310 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2311 b43_set_original_gains(dev);
2319 b43_radio_unlock(dev);
2320 b43_phy_unlock(dev);
2354 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2363 b43err(dev->wl, "Could not allocate memory "
2370 b43err(dev->wl, "Could not generate "
2381 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2383 struct b43_phy *phy = &dev->phy;
2387 pab0 = (s16) (dev->dev->bus_sprom->pa0b0);
2388 pab1 = (s16) (dev->dev->bus_sprom->pa0b1);
2389 pab2 = (s16) (dev->dev->bus_sprom->pa0b2);
2391 B43_WARN_ON((dev->dev->chip_id == 0x4301) &&
2399 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 &&
2400 (s8) dev->dev->bus_sprom->itssi_bg != -1) {
2402 (s8) (dev->dev->bus_sprom->itssi_bg);
2405 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2419 static int b43_gphy_op_allocate(struct b43_wldev *dev)
2430 dev->phy.g = gphy;
2439 err = b43_gphy_init_tssi2dbm_table(dev);
2453 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2455 struct b43_phy *phy = &dev->phy;
2500 static void b43_gphy_op_free(struct b43_wldev *dev)
2502 struct b43_phy *phy = &dev->phy;
2513 dev->phy.g = NULL;
2516 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2518 struct b43_phy *phy = &dev->phy;
2524 default_baseband_attenuation(dev, &gphy->bbatt);
2525 default_radio_attenuation(dev, &gphy->rfatt);
2526 gphy->tx_control = (default_tx_control(dev) << 4);
2527 generate_rfatt_list(dev, &lo->rfatt_list);
2528 generate_bbatt_list(dev, &lo->bbatt_list);
2531 b43_read32(dev, B43_MMIO_MACCTL);
2537 b43_wireless_core_reset(dev, 0);
2538 b43_phy_initg(dev);
2540 b43_wireless_core_reset(dev, 1);
2546 static int b43_gphy_op_init(struct b43_wldev *dev)
2548 b43_phy_initg(dev);
2553 static void b43_gphy_op_exit(struct b43_wldev *dev)
2555 b43_lo_g_cleanup(dev);
2558 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2560 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
2561 return b43_read16(dev, B43_MMIO_PHY_DATA);
2564 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2566 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
2567 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2570 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2577 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
2578 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2581 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2586 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
2587 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2590 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2592 return (dev->phy.rev >= 6);
2595 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2598 struct b43_phy *phy = &dev->phy;
2609 b43_phy_write(dev, 0x0015, 0x8000);
2610 b43_phy_write(dev, 0x0015, 0xCC00);
2611 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2614 b43_phy_write(dev, B43_PHY_RFOVER,
2616 b43_phy_write(dev, B43_PHY_RFOVERVAL,
2621 b43_gphy_channel_switch(dev, 6, 1);
2622 b43_gphy_channel_switch(dev, channel, 0);
2627 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2628 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2632 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2633 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2637 static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2642 b43_gphy_channel_switch(dev, new_channel, 0);
2647 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2652 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2654 struct b43_phy *phy = &dev->phy;
2661 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
2663 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,
2668 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2673 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2676 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2681 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2684 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV);
2686 b43_phy_mask(dev, B43_PHY_ANTWRSETT,
2691 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10);
2692 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15);
2695 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);
2697 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);
2700 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2702 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
2705 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2708 struct b43_phy *phy = &dev->phy;
2737 b43_radio_interference_mitigation_disable(dev, currentmode);
2743 b43_radio_interference_mitigation_enable(dev, mode);
2752 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2754 struct b43_phy_g *gphy = dev->phy.g;
2765 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2770 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2818 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2820 struct b43_phy *phy = &dev->phy;
2825 b43_mac_suspend(dev);
2833 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2843 } else if (dev->dev->bus_sprom->
2862 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2866 if (b43_debug(dev, B43_DBG_XMITPOWER))
2867 b43dbg(dev->wl, "Adjusting TX power\n");
2870 b43_phy_lock(dev);
2871 b43_radio_lock(dev);
2872 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
2874 b43_radio_unlock(dev);
2875 b43_phy_unlock(dev);
2877 b43_mac_enable(dev);
2880 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2883 struct b43_phy *phy = &dev->phy;
2892 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
2893 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
2914 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2917 max_pwr = dev->dev->bus_sprom->maxpwr_bg;
2918 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2921 b43warn(dev->wl,
2924 dev->dev->bus_sprom->maxpwr_bg = max_pwr;
2934 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2935 b43dbg(dev->wl,
2963 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2965 b43dbg(dev->wl,
2988 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
2990 struct b43_phy *phy = &dev->phy;
2993 b43_mac_suspend(dev);
2998 phy->ops->interf_mitigation(dev,
3002 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3003 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3009 b43_lo_g_maintenance_work(dev);
3010 b43_mac_enable(dev);
3013 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3015 struct b43_phy *phy = &dev->phy;
3017 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI))
3020 b43_mac_suspend(dev);
3021 b43_calc_nrssi_slope(dev);
3027 b43_switch_channel(dev, 1);
3029 b43_switch_channel(dev, 13);
3030 b43_switch_channel(dev, old_chan);
3032 b43_mac_enable(dev);