Lines Matching refs:wil
75 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
77 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
81 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil)
83 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS),
87 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
89 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
93 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil)
95 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS),
99 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
101 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
104 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
108 void wil6210_mask_halp(struct wil6210_priv *wil)
110 wil_dbg_irq(wil, "mask_halp\n");
112 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
116 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
118 wil_dbg_irq(wil, "mask_irq_pseudo\n");
120 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
122 clear_bit(wil_status_irqen, wil->status);
125 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
127 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
131 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil)
133 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC),
137 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0;
141 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
145 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil)
147 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC),
151 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
153 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
156 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
160 static void wil6210_unmask_halp(struct wil6210_priv *wil)
162 wil_dbg_irq(wil, "unmask_halp\n");
164 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
168 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
170 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
172 set_bit(wil_status_irqen, wil->status);
174 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
177 void wil_mask_irq(struct wil6210_priv *wil)
179 wil_dbg_irq(wil, "mask_irq\n");
181 wil6210_mask_irq_tx(wil);
182 if (wil->use_enhanced_dma_hw)
183 wil6210_mask_irq_tx_edma(wil);
184 wil6210_mask_irq_rx(wil);
185 if (wil->use_enhanced_dma_hw)
186 wil6210_mask_irq_rx_edma(wil);
187 wil6210_mask_irq_misc(wil, true);
188 wil6210_mask_irq_pseudo(wil);
191 void wil_unmask_irq(struct wil6210_priv *wil)
193 wil_dbg_irq(wil, "unmask_irq\n");
195 if (wil->use_enhanced_dma_hw) {
196 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
198 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
201 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
203 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),
205 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),
208 wil6210_unmask_irq_pseudo(wil);
209 if (wil->use_enhanced_dma_hw) {
210 wil6210_unmask_irq_tx_edma(wil);
211 wil6210_unmask_irq_rx_edma(wil);
213 wil6210_unmask_irq_tx(wil);
214 wil6210_unmask_irq_rx(wil);
216 wil6210_unmask_irq_misc(wil, true);
219 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil)
223 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC);
225 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES);
228 moderation = wil->rx_max_burst_duration |
230 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation);
231 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation);
236 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE);
237 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1);
240 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
242 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr;
244 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
253 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
254 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
255 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
256 wil->tx_max_burst_duration);
258 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
262 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
263 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
264 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
265 wil->tx_interframe_timeout);
267 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
271 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
272 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
273 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
274 wil->rx_max_burst_duration);
276 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
280 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
281 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
282 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
283 wil->rx_interframe_timeout);
285 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
291 struct wil6210_priv *wil = cookie;
295 wil6210_mask_irq_rx(wil);
297 isr = wil_ioread32_and_clear(wil->csr +
302 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
305 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
306 wil6210_unmask_irq_rx(wil);
318 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
323 if (likely(test_bit(wil_status_fwready, wil->status))) {
324 if (likely(test_bit(wil_status_napi_en, wil->status))) {
325 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
327 napi_schedule(&wil->napi_rx);
330 wil,
334 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
339 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
343 atomic_inc(&wil->isr_count_rx);
346 wil6210_unmask_irq_rx(wil);
353 struct wil6210_priv *wil = cookie;
357 wil6210_mask_irq_rx_edma(wil);
359 isr = wil_ioread32_and_clear(wil->csr +
364 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
367 wil_err(wil, "spurious IRQ: RX\n");
368 wil6210_unmask_irq_rx_edma(wil);
373 wil_dbg_irq(wil, "RX status ring\n");
375 if (likely(test_bit(wil_status_fwready, wil->status))) {
376 if (likely(test_bit(wil_status_napi_en, wil->status))) {
377 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
379 napi_schedule(&wil->napi_rx);
381 wil_err(wil,
385 wil_err(wil, "Got Rx interrupt while in reset\n");
390 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
394 atomic_inc(&wil->isr_count_rx);
397 wil6210_unmask_irq_rx_edma(wil);
404 struct wil6210_priv *wil = cookie;
408 wil6210_mask_irq_tx_edma(wil);
410 isr = wil_ioread32_and_clear(wil->csr +
415 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
418 wil_err(wil, "spurious IRQ: TX\n");
419 wil6210_unmask_irq_tx_edma(wil);
424 wil_dbg_irq(wil, "TX status ring\n");
426 if (likely(test_bit(wil_status_fwready, wil->status))) {
427 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
429 napi_schedule(&wil->napi_tx);
431 wil_err(wil, "Got Tx status ring IRQ while in reset\n");
436 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
440 atomic_inc(&wil->isr_count_tx);
443 wil6210_unmask_irq_tx_edma(wil);
450 struct wil6210_priv *wil = cookie;
454 wil6210_mask_irq_tx(wil);
456 isr = wil_ioread32_and_clear(wil->csr +
461 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
464 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
465 wil6210_unmask_irq_tx(wil);
470 wil_dbg_irq(wil, "TX done\n");
474 if (likely(test_bit(wil_status_fwready, wil->status))) {
475 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
477 napi_schedule(&wil->napi_tx);
479 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
484 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
489 atomic_inc(&wil->isr_count_tx);
492 wil6210_unmask_irq_tx(wil);
497 static void wil_notify_fw_error(struct wil6210_priv *wil)
499 struct device *dev = &wil->main_ndev->dev;
505 wil_err(wil, "Notify about firmware error\n");
509 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
512 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
514 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
515 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
518 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
523 if (wil->mbox_ctl.rx.entry_size < min_size) {
524 wil_err(wil, "rx mbox entry too small (%d)\n",
525 wil->mbox_ctl.rx.entry_size);
528 if (wil->mbox_ctl.tx.entry_size < min_size) {
529 wil_err(wil, "tx mbox entry too small (%d)\n",
530 wil->mbox_ctl.tx.entry_size);
539 struct wil6210_priv *wil = cookie;
542 wil6210_mask_irq_misc(wil, false);
544 isr = wil_ioread32_and_clear(wil->csr +
549 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
552 wil_err(wil, "spurious IRQ: MISC\n");
553 wil6210_unmask_irq_misc(wil, false);
558 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr);
560 wil_r(wil, wil->rgf_ucode_assert_code_addr);
562 wil_err(wil,
565 clear_bit(wil_status_fwready, wil->status);
574 wil_dbg_irq(wil, "IRQ: FW ready\n");
575 wil_cache_mbox_regs(wil);
576 if (wil_validate_mbox_regs(wil))
577 set_bit(wil_status_mbox_ready, wil->status);
587 if (wil->halp.handle_icr) {
589 wil->halp.handle_icr = false;
590 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
591 wil6210_mask_irq_misc(wil, true);
592 complete(&wil->halp.comp);
596 wil->isr_misc = isr;
601 wil6210_unmask_irq_misc(wil, false);
608 struct wil6210_priv *wil = cookie;
609 u32 isr = wil->isr_misc;
612 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
615 wil->recovery_state = fw_recovery_pending;
616 wil_fw_core_dump(wil);
617 wil_notify_fw_error(wil);
619 if (wil->platform_ops.notify) {
620 wil_err(wil, "notify platform driver about FW crash");
621 wil->platform_ops.notify(wil->platform_handle,
624 wil_fw_error_recovery(wil);
628 wil_dbg_irq(wil, "MBOX event\n");
629 wmi_recv_cmd(wil);
634 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
636 wil->isr_misc = 0;
638 wil6210_unmask_irq_misc(wil, false);
643 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) {
644 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
645 wil->suspend_resp_comp = true;
646 wake_up_interruptible(&wil->wq);
655 struct wil6210_priv *wil = cookie;
657 wil_dbg_irq(wil, "Thread IRQ\n");
659 if (wil->isr_misc)
662 wil6210_unmask_irq_pseudo(wil);
664 if (wil->suspend_resp_rcvd) {
665 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
666 wil->suspend_resp_comp = true;
667 wake_up_interruptible(&wil->wq);
679 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
685 if (!test_bit(wil_status_irqen, wil->status)) {
686 if (wil->use_enhanced_dma_hw) {
687 icm_rx = wil_ioread32_and_clear(wil->csr +
690 icr_rx = wil_ioread32_and_clear(wil->csr +
693 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR +
695 icm_tx = wil_ioread32_and_clear(wil->csr +
698 icr_tx = wil_ioread32_and_clear(wil->csr +
701 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR +
704 icm_rx = wil_ioread32_and_clear(wil->csr +
707 icr_rx = wil_ioread32_and_clear(wil->csr +
710 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
712 icm_tx = wil_ioread32_and_clear(wil->csr +
715 icr_tx = wil_ioread32_and_clear(wil->csr +
718 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
721 icm_misc = wil_ioread32_and_clear(wil->csr +
724 icr_misc = wil_ioread32_and_clear(wil->csr +
727 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
736 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
754 struct wil6210_priv *wil = cookie;
755 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
764 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
768 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
770 wil6210_mask_irq_pseudo(wil);
786 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
790 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
799 wil6210_unmask_irq_pseudo(wil);
804 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
813 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED,
814 WIL_NAME "_tx", wil);
818 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED,
819 WIL_NAME "_rx", wil);
825 IRQF_SHARED, WIL_NAME "_misc", wil);
831 free_irq(irq + 1, wil);
833 free_irq(irq, wil);
846 void wil6210_clear_irq(struct wil6210_priv *wil)
848 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
850 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
852 if (wil->use_enhanced_dma_hw) {
853 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) +
855 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) +
858 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
863 void wil6210_set_halp(struct wil6210_priv *wil)
865 wil_dbg_irq(wil, "set_halp\n");
867 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
871 void wil6210_clear_halp(struct wil6210_priv *wil)
873 wil_dbg_irq(wil, "clear_halp\n");
875 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
877 wil6210_unmask_halp(wil);
880 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
884 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n",
885 wil->n_msi ? "MSI" : "INTx", wil->n_msi);
887 if (wil->use_enhanced_dma_hw) {
888 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma;
889 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma;
891 wil->txrx_ops.irq_tx = wil6210_irq_tx;
892 wil->txrx_ops.irq_rx = wil6210_irq_rx;
895 if (wil->n_msi == 3)
896 rc = wil6210_request_3msi(wil, irq);
900 wil->n_msi ? 0 : IRQF_SHARED,
901 WIL_NAME, wil);
905 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
907 wil_dbg_misc(wil, "fini_irq:\n");
909 wil_mask_irq(wil);
910 free_irq(irq, wil);
911 if (wil->n_msi == 3) {
912 free_irq(irq + 1, wil);
913 free_irq(irq + 2, wil);