Lines Matching defs:ah
34 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
72 struct ath_common *common = ath9k_hw_common(ah);
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
84 if ((REG_READ(ah, reg) & mask) == val)
90 ath_dbg(ath9k_hw_common(ah), ANY,
92 timeout, reg, REG_READ(ah, reg), mask, val);
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
116 ENABLE_REGWRITE_BUFFER(ah);
118 REG_WRITE(ah, INI_RA(array, r, 0),
122 REGWRITE_BUFFER_FLUSH(ah);
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
194 } else if (ah->curchan &&
195 IS_CHAN_HALF_RATE(ah->curchan)) {
212 ath_err(ath9k_hw_common(ah),
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
255 static bool ath9k_hw_read_revisions(struct ath_hw *ah)
260 if (ah->get_mac_revision)
261 ah->hw_version.macRev = ah->get_mac_revision();
263 switch (ah->hw_version.devid) {
265 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
268 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
269 if (!ah->get_mac_revision) {
270 val = REG_READ(ah, AR_SREV(ah));
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
278 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
281 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
284 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
288 srev = REG_READ(ah, AR_SREV(ah));
291 ath_err(ath9k_hw_common(ah),
296 val = srev & AR_SREV_ID(ah);
300 ah->hw_version.macVersion =
302 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
304 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
305 ah->is_pciexpress = true;
307 ah->is_pciexpress = (val &
310 if (!AR_SREV_9100(ah))
311 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
313 ah->hw_version.macRev = val & AR_SREV_REVISION;
315 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
316 ah->is_pciexpress = true;
326 static void ath9k_hw_disablepcie(struct ath_hw *ah)
328 if (!AR_SREV_5416(ah))
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
338 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
341 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
345 static bool ath9k_hw_chip_test(struct ath_hw *ah)
347 struct ath_common *common = ath9k_hw_common(ah);
355 if (!AR_SREV_9300_20_OR_LATER(ah)) {
365 regHold[i] = REG_READ(ah, addr);
368 REG_WRITE(ah, addr, wrData);
369 rdData = REG_READ(ah, addr);
379 REG_WRITE(ah, addr, wrData);
380 rdData = REG_READ(ah, addr);
388 REG_WRITE(ah, regAddr[i], regHold[i]);
395 static void ath9k_hw_init_config(struct ath_hw *ah)
397 struct ath_common *common = ath9k_hw_common(ah);
399 ah->config.dma_beacon_response_time = 1;
400 ah->config.sw_beacon_response_time = 6;
401 ah->config.cwm_ignore_extcca = false;
402 ah->config.analog_shiftreg = 1;
404 ah->config.rx_intr_mitigation = true;
406 if (AR_SREV_9300_20_OR_LATER(ah)) {
407 ah->config.rimt_last = 500;
408 ah->config.rimt_first = 2000;
410 ah->config.rimt_last = 250;
411 ah->config.rimt_first = 700;
414 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
415 ah->config.pll_pwrsave = 7;
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
436 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
437 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
438 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
439 !ah->is_pciexpress)) {
440 ah->config.serialize_regmode = SER_REG_MODE_ON;
442 ah->config.serialize_regmode = SER_REG_MODE_OFF;
447 ah->config.serialize_regmode);
449 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
450 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
452 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
455 static void ath9k_hw_init_defaults(struct ath_hw *ah)
457 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
462 ah->hw_version.magic = AR5416_MAGIC;
463 ah->hw_version.subvendorid = 0;
465 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
467 if (AR_SREV_9100(ah))
468 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
470 ah->slottime = 9;
471 ah->globaltxtimeout = (u32) -1;
472 ah->power_mode = ATH9K_PM_UNDEFINED;
473 ah->htc_reset_init = true;
475 ah->tpc_enabled = false;
477 ah->ani_function = ATH9K_ANI_ALL;
478 if (!AR_SREV_9300_20_OR_LATER(ah))
479 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
481 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
482 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
484 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
487 static void ath9k_hw_init_macaddr(struct ath_hw *ah)
489 struct ath_common *common = ath9k_hw_common(ah);
499 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
517 static int ath9k_hw_post_init(struct ath_hw *ah)
519 struct ath_common *common = ath9k_hw_common(ah);
523 if (!ath9k_hw_chip_test(ah))
527 if (!AR_SREV_9300_20_OR_LATER(ah)) {
528 ecode = ar9002_hw_rf_claim(ah);
533 ecode = ath9k_hw_eeprom_init(ah);
537 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
538 ah->eep_ops->get_eeprom_ver(ah),
539 ah->eep_ops->get_eeprom_rev(ah));
541 ath9k_hw_ani_init(ah);
547 if (AR_SREV_9300_20_OR_LATER(ah)) {
548 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
550 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
551 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
558 static int ath9k_hw_attach_ops(struct ath_hw *ah)
560 if (!AR_SREV_9300_20_OR_LATER(ah))
561 return ar9002_hw_attach_ops(ah);
563 ar9003_hw_attach_ops(ah);
568 static int __ath9k_hw_init(struct ath_hw *ah)
570 struct ath_common *common = ath9k_hw_common(ah);
573 if (!ath9k_hw_read_revisions(ah)) {
578 switch (ah->hw_version.macVersion) {
600 ah->hw_version.macVersion, ah->hw_version.macRev);
605 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17.
609 if (AR_SREV_9300_20_OR_LATER(ah)) {
610 ah->WARegVal = REG_READ(ah, AR_WA(ah));
611 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
615 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
620 if (AR_SREV_9565(ah)) {
621 ah->WARegVal |= AR_WA_BIT22;
622 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
625 ath9k_hw_init_defaults(ah);
626 ath9k_hw_init_config(ah);
628 r = ath9k_hw_attach_ops(ah);
632 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
637 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
638 AR_SREV_9330(ah) || AR_SREV_9550(ah))
639 ah->is_pciexpress = false;
641 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
642 ath9k_hw_init_cal_settings(ah);
644 if (!ah->is_pciexpress)
645 ath9k_hw_disablepcie(ah);
647 r = ath9k_hw_post_init(ah);
651 ath9k_hw_init_mode_gain_regs(ah);
652 r = ath9k_hw_fill_cap_info(ah);
656 ath9k_hw_init_macaddr(ah);
657 ath9k_hw_init_hang_checks(ah);
664 int ath9k_hw_init(struct ath_hw *ah)
667 struct ath_common *common = ath9k_hw_common(ah);
670 switch (ah->hw_version.devid) {
697 ah->hw_version.devid);
701 ret = __ath9k_hw_init(ah);
709 ath_dynack_init(ah);
715 static void ath9k_hw_init_qos(struct ath_hw *ah)
717 ENABLE_REGWRITE_BUFFER(ah);
719 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
720 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
722 REG_WRITE(ah, AR_QOS_NO_ACK,
727 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
728 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
729 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
730 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
731 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
733 REGWRITE_BUFFER_FLUSH(ah);
736 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
738 struct ath_common *common = ath9k_hw_common(ah);
741 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
743 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
745 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
757 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
761 static void ath9k_hw_init_pll(struct ath_hw *ah,
766 pll = ath9k_hw_compute_pll_control(ah, chan);
768 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
792 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
798 } else if (AR_SREV_9330(ah)) {
801 if (ah->is_clk_25mhz) {
812 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
815 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
818 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
823 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
832 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
833 AR_SREV_9561(ah)) {
836 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
840 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
843 if (ah->is_clk_25mhz) {
844 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
854 if (AR_SREV_9340(ah)) {
860 pll2_divfrac = (AR_SREV_9531(ah) ||
861 AR_SREV_9561(ah)) ?
867 regval = REG_READ(ah, AR_PHY_PLL_MODE);
868 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
872 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
875 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
879 regval = REG_READ(ah, AR_PHY_PLL_MODE);
880 if (AR_SREV_9340(ah))
886 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
893 if (AR_SREV_9531(ah))
901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
903 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
904 REG_WRITE(ah, AR_PHY_PLL_MODE,
905 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
907 REG_WRITE(ah, AR_PHY_PLL_MODE,
908 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
913 if (AR_SREV_9565(ah))
915 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);
917 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
918 AR_SREV_9550(ah))
922 if (AR_SREV_9271(ah)) {
924 REG_WRITE(ah, 0x50040, 0x304);
929 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK);
932 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
943 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
944 AR_SREV_9561(ah))
947 if (AR_SREV_9300_20_OR_LATER(ah)) {
949 if (ah->config.rx_intr_mitigation) {
957 if (ah->config.rx_intr_mitigation) {
966 if (ah->config.tx_intr_mitigation) {
974 ENABLE_REGWRITE_BUFFER(ah);
976 REG_WRITE(ah, AR_IMR, imr_reg);
977 ah->imrs2_reg |= AR_IMR_S2_GTT;
978 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
980 if (ah->msi_enabled) {
981 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));
982 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
983 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
984 REG_WRITE(ah, AR_INTCFG, msi_cfg);
985 ath_dbg(ath9k_hw_common(ah), ANY,
987 REG_READ(ah, AR_INTCFG), msi_cfg);
990 if (!AR_SREV_9100(ah)) {
991 REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF);
992 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);
993 REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0);
996 REGWRITE_BUFFER_FLUSH(ah);
998 if (AR_SREV_9300_20_OR_LATER(ah)) {
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);
1000 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0);
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0);
1002 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0);
1006 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1008 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1010 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1013 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1015 u32 val = ath9k_hw_mac_to_clks(ah, us);
1017 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1020 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1022 u32 val = ath9k_hw_mac_to_clks(ah, us);
1024 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1027 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1029 u32 val = ath9k_hw_mac_to_clks(ah, us);
1031 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1034 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1037 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1039 ah->globaltxtimeout = (u32) -1;
1042 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1043 ah->globaltxtimeout = tu;
1048 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1050 struct ath_common *common = ath9k_hw_common(ah);
1051 const struct ath9k_channel *chan = ah->curchan;
1058 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1059 ah->misc_mode);
1064 if (ah->misc_mode != 0)
1065 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1067 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1093 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1101 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1105 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1107 reg = REG_READ(ah, AR_USEC);
1112 slottime = ah->slottime;
1116 slottime += 3 * ah->coverage_class;
1129 acktimeout += 64 - sifstime - ah->slottime;
1130 ctstimeout += 48 - sifstime - ah->slottime;
1133 if (ah->dynack.enabled) {
1134 acktimeout = ah->dynack.ackto;
1138 ah->dynack.ackto = acktimeout;
1141 ath9k_hw_set_sifs_time(ah, sifstime);
1142 ath9k_hw_setslottime(ah, slottime);
1143 ath9k_hw_set_ack_timeout(ah, acktimeout);
1144 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1145 if (ah->globaltxtimeout != (u32) -1)
1146 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1148 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1149 REG_RMW(ah, AR_USEC,
1156 REG_RMW(ah, AR_TXSIFS,
1162 void ath9k_hw_deinit(struct ath_hw *ah)
1164 struct ath_common *common = ath9k_hw_common(ah);
1169 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1193 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1195 struct ath_common *common = ath9k_hw_common(ah);
1198 ENABLE_REGWRITE_BUFFER(ah);
1203 if (!AR_SREV_9300_20_OR_LATER(ah))
1204 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1209 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1211 REGWRITE_BUFFER_FLUSH(ah);
1218 if (!AR_SREV_9300_20_OR_LATER(ah))
1219 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1221 ENABLE_REGWRITE_BUFFER(ah);
1226 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1231 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1233 if (AR_SREV_9300_20_OR_LATER(ah)) {
1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1235 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1237 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1238 ah->caps.rx_status_len);
1245 if (AR_SREV_9285(ah)) {
1251 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1258 if (!AR_SREV_9271(ah))
1259 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1261 REGWRITE_BUFFER_FLUSH(ah);
1263 if (AR_SREV_9300_20_OR_LATER(ah))
1264 ath9k_hw_reset_txstatus_ring(ah);
1267 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1272 ENABLE_REG_RMW_BUFFER(ah);
1275 if (!AR_SREV_9340_13(ah)) {
1277 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1287 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1290 if (!ah->is_monitoring)
1294 REG_RMW(ah, AR_STA_ID1, set, mask);
1295 REG_RMW_BUFFER_FLUSH(ah);
1298 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1320 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1325 npend = ath9k_hw_numtxpending(ah, i);
1330 if (ah->external_reset &&
1334 ath_dbg(ath9k_hw_common(ah), RESET,
1337 reset_err = ah->external_reset();
1339 ath_err(ath9k_hw_common(ah),
1345 REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1351 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1356 if (AR_SREV_9100(ah)) {
1357 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK(ah),
1359 (void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah));
1362 ENABLE_REGWRITE_BUFFER(ah);
1364 if (AR_SREV_9300_20_OR_LATER(ah)) {
1365 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1369 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1372 if (AR_SREV_9100(ah)) {
1376 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));
1377 if (AR_SREV_9340(ah))
1385 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);
1388 if (!AR_SREV_9300_20_OR_LATER(ah))
1390 REG_WRITE(ah, AR_RC, val);
1392 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1393 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1400 if (AR_SREV_9330(ah)) {
1401 if (!ath9k_hw_ar9330_reset_war(ah, type))
1405 if (ath9k_hw_mci_is_enabled(ah))
1406 ar9003_mci_check_gpm_offset(ah);
1411 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1412 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1413 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1415 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1418 REG_WRITE(ah, AR_RTC_RC(ah), rst_flags);
1420 REGWRITE_BUFFER_FLUSH(ah);
1422 if (AR_SREV_9300_20_OR_LATER(ah))
1424 else if (AR_SREV_9100(ah))
1429 REG_WRITE(ah, AR_RTC_RC(ah), 0);
1430 if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1431 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1435 if (!AR_SREV_9100(ah))
1436 REG_WRITE(ah, AR_RC, 0);
1438 if (AR_SREV_9100(ah))
1444 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1446 ENABLE_REGWRITE_BUFFER(ah);
1448 if (AR_SREV_9300_20_OR_LATER(ah)) {
1449 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1453 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1456 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1457 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1459 REG_WRITE(ah, AR_RTC_RESET(ah), 0);
1461 REGWRITE_BUFFER_FLUSH(ah);
1465 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1466 REG_WRITE(ah, AR_RC, 0);
1468 REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1470 if (!ath9k_hw_wait(ah,
1471 AR_RTC_STATUS(ah),
1472 AR_RTC_STATUS_M(ah),
1475 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1479 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1482 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1486 if (AR_SREV_9300_20_OR_LATER(ah)) {
1487 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1491 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
1494 if (!ah->reset_power_on)
1499 ret = ath9k_hw_set_reset_power_on(ah);
1501 ah->reset_power_on = true;
1505 ret = ath9k_hw_set_reset(ah, type);
1514 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1519 if (AR_SREV_9280(ah)) {
1520 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1524 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1525 (REG_READ(ah, AR_CR) & AR_CR_RXE(ah)))
1528 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1531 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1534 ah->chip_fullsleep = false;
1536 if (AR_SREV_9330(ah))
1537 ar9003_hw_internal_regulator_apply(ah);
1538 ath9k_hw_init_pll(ah, chan);
1543 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1546 struct ath_common *common = ath9k_hw_common(ah);
1547 struct ath9k_hw_capabilities *pCap = &ah->caps;
1554 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1560 if (ath9k_hw_numtxpending(ah, qnum)) {
1567 if (!ath9k_hw_rfbus_req(ah)) {
1573 ath9k_hw_mark_phy_inactive(ah);
1577 ath9k_hw_init_pll(ah, chan);
1579 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1585 ath9k_hw_set_channel_regs(ah, chan);
1587 r = ath9k_hw_rf_set_freq(ah, chan);
1592 ath9k_hw_set_clockrate(ah);
1593 ath9k_hw_apply_txpower(ah, chan, false);
1595 ath9k_hw_set_delta_slope(ah, chan);
1596 ath9k_hw_spur_mitigate_freq(ah, chan);
1599 ah->eep_ops->set_board_values(ah, chan);
1601 ath9k_hw_init_bb(ah, chan);
1602 ath9k_hw_rfbus_done(ah);
1605 ah->ah_flags |= AH_FASTCC;
1606 ath9k_hw_init_cal(ah, chan);
1607 ah->ah_flags &= ~AH_FASTCC;
1613 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1615 u32 gpio_mask = ah->gpio_mask;
1622 ath9k_hw_gpio_request_out(ah, i, NULL,
1624 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1628 void ath9k_hw_check_nav(struct ath_hw *ah)
1630 struct ath_common *common = ath9k_hw_common(ah);
1633 val = REG_READ(ah, AR_NAV);
1636 REG_WRITE(ah, AR_NAV, 0);
1641 bool ath9k_hw_check_alive(struct ath_hw *ah)
1647 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1650 if (AR_SREV_9300(ah))
1651 return !ath9k_hw_detect_mac_hang(ah);
1653 if (AR_SREV_9285_12_OR_LATER(ah))
1656 last_val = REG_READ(ah, AR_OBS_BUS_1);
1658 reg = REG_READ(ah, AR_OBS_BUS_1);
1681 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1684 if (AR_SREV_9280_20_OR_LATER(ah)) {
1687 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1689 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1690 ah->sw_mgmt_crypto_tx = true;
1692 ah->sw_mgmt_crypto_tx = false;
1693 ah->sw_mgmt_crypto_rx = false;
1694 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1696 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1698 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1700 ah->sw_mgmt_crypto_tx = true;
1701 ah->sw_mgmt_crypto_rx = true;
1703 ah->sw_mgmt_crypto_tx = true;
1704 ah->sw_mgmt_crypto_rx = true;
1708 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1711 struct ath_common *common = ath9k_hw_common(ah);
1713 ENABLE_REGWRITE_BUFFER(ah);
1715 REG_RMW(ah, AR_STA_ID1, macStaId1
1717 | ah->sta_id1_defaults,
1720 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1721 ath9k_hw_write_associd(ah);
1722 REG_WRITE(ah, AR_ISR, ~0);
1723 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1725 REGWRITE_BUFFER_FLUSH(ah);
1727 ath9k_hw_set_operating_mode(ah, ah->opmode);
1730 static void ath9k_hw_init_queues(struct ath_hw *ah)
1734 ENABLE_REGWRITE_BUFFER(ah);
1737 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1739 REGWRITE_BUFFER_FLUSH(ah);
1741 ah->intr_txqs = 0;
1743 ath9k_hw_resettxqueue(ah, i);
1749 static void ath9k_hw_init_desc(struct ath_hw *ah)
1751 struct ath_common *common = ath9k_hw_common(ah);
1753 if (AR_SREV_9100(ah)) {
1755 mask = REG_READ(ah, AR_CFG);
1761 REG_WRITE(ah, AR_CFG, mask);
1763 REG_READ(ah, AR_CFG));
1768 if (AR_SREV_9271(ah))
1769 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1771 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1774 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1775 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1776 AR_SREV_9561(ah))
1777 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1779 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1788 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1790 struct ath_common *common = ath9k_hw_common(ah);
1791 struct ath9k_hw_capabilities *pCap = &ah->caps;
1794 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1797 if (ah->chip_fullsleep)
1800 if (!ah->curchan)
1803 if (chan->channel == ah->curchan->channel)
1806 if ((ah->curchan->channelFlags | chan->channelFlags) &
1814 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1817 if (!ath9k_hw_check_alive(ah))
1824 if (AR_SREV_9462(ah) && (ah->caldata &&
1825 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1826 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1827 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1831 ah->curchan->channel, chan->channel);
1833 ret = ath9k_hw_channel_change(ah, chan);
1837 if (ath9k_hw_mci_is_enabled(ah))
1838 ar9003_mci_2g5g_switch(ah, false);
1840 ath9k_hw_loadnf(ah, ah->curchan);
1841 ath9k_hw_start_nfcal(ah, true);
1843 if (AR_SREV_9271(ah))
1844 ar9002_hw_load_ani_reg(ah, chan);
1859 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1862 struct ath_common *common = ath9k_hw_common(ah);
1871 bool save_fullsleep = ah->chip_fullsleep;
1873 if (ath9k_hw_mci_is_enabled(ah)) {
1874 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1879 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1882 if (ah->curchan && !ah->chip_fullsleep)
1883 ath9k_hw_getnf(ah, ah->curchan);
1885 ah->caldata = caldata;
1890 ath9k_init_nfcal_hist_buffer(ah, chan);
1894 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1897 r = ath9k_hw_do_fastcc(ah, chan);
1902 if (ath9k_hw_mci_is_enabled(ah))
1903 ar9003_mci_stop_bt(ah, save_fullsleep);
1905 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1909 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1913 tsf = ath9k_hw_gettsf64(ah);
1915 saveLedState = REG_READ(ah, AR_CFG_LED) &
1919 ath9k_hw_mark_phy_inactive(ah);
1921 ah->paprd_table_write_done = false;
1924 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1925 REG_WRITE(ah,
1931 if (!ath9k_hw_chip_reset(ah, chan)) {
1937 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1938 ah->htc_reset_init = false;
1939 REG_WRITE(ah,
1947 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1949 if (AR_SREV_9280_20_OR_LATER(ah))
1950 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
1952 if (!AR_SREV_9300_20_OR_LATER(ah))
1953 ar9002_hw_enable_async_fifo(ah);
1955 r = ath9k_hw_process_ini(ah, chan);
1959 ath9k_hw_set_rfmode(ah, chan);
1961 if (ath9k_hw_mci_is_enabled(ah))
1962 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1969 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1971 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1974 ath9k_hw_init_mfp(ah);
1976 ath9k_hw_set_delta_slope(ah, chan);
1977 ath9k_hw_spur_mitigate_freq(ah, chan);
1978 ah->eep_ops->set_board_values(ah, chan);
1980 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1982 r = ath9k_hw_rf_set_freq(ah, chan);
1986 ath9k_hw_set_clockrate(ah);
1988 ath9k_hw_init_queues(ah);
1989 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1990 ath9k_hw_ani_cache_ini_regs(ah);
1991 ath9k_hw_init_qos(ah);
1993 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1994 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
1996 ath9k_hw_init_global_settings(ah);
1998 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1999 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2001 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2003 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2007 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2009 ath9k_hw_set_dma(ah);
2011 if (!ath9k_hw_mci_is_enabled(ah))
2012 REG_WRITE(ah, AR_OBS(ah), 8);
2014 ENABLE_REG_RMW_BUFFER(ah);
2015 if (ah->config.rx_intr_mitigation) {
2016 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2017 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
2020 if (ah->config.tx_intr_mitigation) {
2021 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2022 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2024 REG_RMW_BUFFER_FLUSH(ah);
2026 ath9k_hw_init_bb(ah, chan);
2032 if (!ath9k_hw_init_cal(ah, chan))
2035 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2038 ENABLE_REGWRITE_BUFFER(ah);
2040 ath9k_hw_restore_chainmask(ah);
2041 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2043 REGWRITE_BUFFER_FLUSH(ah);
2045 ath9k_hw_gen_timer_start_tsf2(ah);
2047 ath9k_hw_init_desc(ah);
2049 if (ath9k_hw_btcoex_is_enabled(ah))
2050 ath9k_hw_btcoex_enable(ah);
2052 if (ath9k_hw_mci_is_enabled(ah))
2053 ar9003_mci_check_bt(ah);
2055 if (AR_SREV_9300_20_OR_LATER(ah)) {
2056 ath9k_hw_loadnf(ah, chan);
2057 ath9k_hw_start_nfcal(ah, true);
2060 if (AR_SREV_9300_20_OR_LATER(ah))
2061 ar9003_hw_bb_watchdog_config(ah);
2063 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2064 ar9003_hw_disable_phy_restart(ah);
2066 ath9k_hw_apply_gpio_override(ah);
2068 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2069 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2071 if (ah->hw->conf.radar_enabled) {
2073 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2074 ath9k_hw_set_radar_params(ah);
2089 static void ath9k_set_power_sleep(struct ath_hw *ah)
2091 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2093 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2094 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2095 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2096 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2098 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2106 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2108 if (ath9k_hw_mci_is_enabled(ah))
2111 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2112 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2115 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2116 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN);
2120 /* Clear Bit 14 of AR_WA(ah) after putting chip into Full Sleep mode. */
2121 if (AR_SREV_9300_20_OR_LATER(ah))
2122 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2130 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2132 struct ath9k_hw_capabilities *pCap = &ah->caps;
2134 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2138 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
2151 if (ath9k_hw_mci_is_enabled(ah))
2152 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2158 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2160 if (ath9k_hw_mci_is_enabled(ah))
2164 /* Clear Bit 14 of AR_WA(ah) after putting chip into Net Sleep mode. */
2165 if (AR_SREV_9300_20_OR_LATER(ah))
2166 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2169 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2174 /* Set Bits 14 and 17 of AR_WA(ah) before powering on the chip. */
2175 if (AR_SREV_9300_20_OR_LATER(ah)) {
2176 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
2180 if ((REG_READ(ah, AR_RTC_STATUS(ah)) &
2181 AR_RTC_STATUS_M(ah)) == AR_RTC_STATUS_SHUTDOWN) {
2182 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2185 if (!AR_SREV_9300_20_OR_LATER(ah))
2186 ath9k_hw_init_pll(ah, NULL);
2188 if (AR_SREV_9100(ah))
2189 REG_SET_BIT(ah, AR_RTC_RESET(ah),
2192 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2194 if (AR_SREV_9100(ah))
2200 val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah);
2204 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2208 ath_err(ath9k_hw_common(ah),
2214 if (ath9k_hw_mci_is_enabled(ah))
2215 ar9003_mci_set_power_awake(ah);
2217 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2222 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2224 struct ath_common *common = ath9k_hw_common(ah);
2233 if (ah->power_mode == mode)
2237 modes[ah->power_mode], modes[mode]);
2241 status = ath9k_hw_set_power_awake(ah);
2244 if (ath9k_hw_mci_is_enabled(ah))
2245 ar9003_mci_set_full_sleep(ah);
2247 ath9k_set_power_sleep(ah);
2248 ah->chip_fullsleep = true;
2251 ath9k_set_power_network_sleep(ah);
2257 ah->power_mode = mode;
2265 if (!(ah->ah_flags & AH_UNPLUGGED))
2276 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2280 ENABLE_REGWRITE_BUFFER(ah);
2282 switch (ah->opmode) {
2284 REG_SET_BIT(ah, AR_TXCFG,
2289 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2290 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2291 TU_TO_USEC(ah->config.dma_beacon_response_time));
2292 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2293 TU_TO_USEC(ah->config.sw_beacon_response_time));
2298 ath_dbg(ath9k_hw_common(ah), BEACON,
2299 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2303 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2304 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2305 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2307 REGWRITE_BUFFER_FLUSH(ah);
2309 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2313 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2317 struct ath9k_hw_capabilities *pCap = &ah->caps;
2318 struct ath_common *common = ath9k_hw_common(ah);
2320 ENABLE_REGWRITE_BUFFER(ah);
2322 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2323 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2324 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2326 REGWRITE_BUFFER_FLUSH(ah);
2328 REG_RMW_FIELD(ah, AR_RSSI_THR,
2350 ENABLE_REGWRITE_BUFFER(ah);
2352 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2353 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2355 REG_WRITE(ah, AR_SLEEP1,
2364 REG_WRITE(ah, AR_SLEEP2,
2367 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2368 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2370 REGWRITE_BUFFER_FLUSH(ah);
2372 REG_SET_BIT(ah, AR_TIMER_MODE,
2377 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2396 * @ah: the atheros hardware data structure
2407 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2410 switch (ah->hw_version.macVersion) {
2421 static void ath9k_gpio_cap_init(struct ath_hw *ah)
2423 struct ath9k_hw_capabilities *pCap = &ah->caps;
2425 if (AR_SREV_9271(ah)) {
2428 } else if (AR_DEVID_7010(ah)) {
2431 } else if (AR_SREV_9287(ah)) {
2434 } else if (AR_SREV_9285(ah)) {
2437 } else if (AR_SREV_9280(ah)) {
2440 } else if (AR_SREV_9300(ah)) {
2443 } else if (AR_SREV_9330(ah)) {
2446 } else if (AR_SREV_9340(ah)) {
2449 } else if (AR_SREV_9462(ah)) {
2452 } else if (AR_SREV_9485(ah)) {
2455 } else if (AR_SREV_9531(ah)) {
2458 } else if (AR_SREV_9550(ah)) {
2461 } else if (AR_SREV_9561(ah)) {
2464 } else if (AR_SREV_9565(ah)) {
2467 } else if (AR_SREV_9580(ah)) {
2476 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2478 struct ath9k_hw_capabilities *pCap = &ah->caps;
2479 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2480 struct ath_common *common = ath9k_hw_common(ah);
2485 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2488 if (ah->opmode != NL80211_IFTYPE_AP &&
2489 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2499 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2502 if (ah->disable_5ghz)
2509 if (ah->disable_2ghz)
2520 ath9k_gpio_cap_init(ah);
2522 if (AR_SREV_9485(ah) ||
2523 AR_SREV_9285(ah) ||
2524 AR_SREV_9330(ah) ||
2525 AR_SREV_9565(ah))
2527 else if (!AR_SREV_9280_20_OR_LATER(ah))
2529 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2530 AR_SREV_9340(ah) ||
2531 AR_SREV_9462(ah) ||
2532 AR_SREV_9531(ah))
2537 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2542 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2544 !(AR_SREV_9271(ah)))
2546 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2547 else if (AR_SREV_9100(ah))
2551 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2555 ah->txchainmask = pCap->tx_chainmask;
2556 ah->rxchainmask = pCap->rx_chainmask;
2558 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2561 if (AR_SREV_9300_20_OR_LATER(ah))
2562 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2566 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2571 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2577 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2578 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2579 ah->rfkill_gpio =
2580 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2581 ah->rfkill_polarity =
2582 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2587 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2592 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2597 if (AR_SREV_9300_20_OR_LATER(ah)) {
2599 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2600 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2610 if (AR_SREV_9280_20(ah))
2614 if (AR_SREV_9300_20_OR_LATER(ah))
2617 if (AR_SREV_9561(ah))
2618 ah->ent_mode = 0x3BDA000;
2619 else if (AR_SREV_9300_20_OR_LATER(ah))
2620 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2622 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2625 if (AR_SREV_9285(ah)) {
2626 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2628 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2636 if (AR_SREV_9300_20_OR_LATER(ah)) {
2637 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2641 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2642 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2649 if (ath9k_hw_dfs_tested(ah))
2664 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2665 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2668 if (AR_SREV_9462_20_OR_LATER(ah))
2672 if (AR_SREV_9300_20_OR_LATER(ah) &&
2673 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2677 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2678 ah->wow.max_patterns = MAX_NUM_PATTERN;
2680 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2690 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
2696 addr = AR_GPIO_OUTPUT_MUX3(ah);
2698 addr = AR_GPIO_OUTPUT_MUX2(ah);
2700 addr = AR_GPIO_OUTPUT_MUX1(ah);
2704 if (AR_SREV_9280_20_OR_LATER(ah) ||
2705 (addr != AR_GPIO_OUTPUT_MUX1(ah))) {
2706 REG_RMW(ah, addr, (type << gpio_shift),
2709 tmp = REG_READ(ah, addr);
2713 REG_WRITE(ah, addr, tmp);
2719 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2724 if (ah->caps.gpio_requested & BIT(gpio))
2727 err = devm_gpio_request_one(ah->dev, gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label);
2729 ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n",
2734 ah->caps.gpio_requested |= BIT(gpio);
2737 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2742 if (AR_DEVID_7010(ah)) {
2745 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2747 } else if (AR_SREV_SOC(ah)) {
2749 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2755 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2759 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2763 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2766 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2768 if (BIT(gpio) & ah->caps.gpio_mask)
2769 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2770 else if (AR_SREV_SOC(ah))
2771 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2776 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2778 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2782 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2785 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2789 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2791 if (!AR_SREV_SOC(ah))
2794 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2796 if (ah->caps.gpio_requested & BIT(gpio))
2797 ah->caps.gpio_requested &= ~BIT(gpio);
2801 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2806 (MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y))
2808 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2810 if (BIT(gpio) & ah->caps.gpio_mask) {
2811 if (AR_SREV_9271(ah))
2813 else if (AR_SREV_9287(ah))
2815 else if (AR_SREV_9285(ah))
2817 else if (AR_SREV_9280(ah))
2819 else if (AR_DEVID_7010(ah))
2820 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2821 else if (AR_SREV_9300_20_OR_LATER(ah))
2822 val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio);
2825 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2835 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2837 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2839 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2844 if (BIT(gpio) & ah->caps.gpio_mask) {
2845 u32 out_addr = AR_DEVID_7010(ah) ?
2846 AR7010_GPIO_OUT : AR_GPIO_IN_OUT(ah);
2848 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2849 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2857 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2859 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2867 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2869 u32 bits = REG_READ(ah, AR_RX_FILTER);
2870 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2881 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2885 ENABLE_REGWRITE_BUFFER(ah);
2887 REG_WRITE(ah, AR_RX_FILTER, bits);
2894 REG_WRITE(ah, AR_PHY_ERR, phybits);
2897 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2899 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2901 REGWRITE_BUFFER_FLUSH(ah);
2905 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2907 if (ath9k_hw_mci_is_enabled(ah))
2908 ar9003_mci_bt_gain_ctrl(ah);
2910 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2913 ath9k_hw_init_pll(ah, NULL);
2914 ah->htc_reset_init = true;
2919 bool ath9k_hw_disable(struct ath_hw *ah)
2921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2924 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2927 ath9k_hw_init_pll(ah, NULL);
2932 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2941 return ah->eep_ops->get_eeprom(ah, gain_param);
2944 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2947 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2962 ah->eep_ops->set_txpower(ah, chan, ctl,
2963 get_antenna_gain(ah, chan), new_pwr, test);
2966 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2968 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2969 struct ath9k_channel *chan = ah->curchan;
2976 ath9k_hw_apply_txpower(ah, chan, test);
2983 void ath9k_hw_setopmode(struct ath_hw *ah)
2985 ath9k_hw_set_operating_mode(ah, ah->opmode);
2989 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2991 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2992 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2996 void ath9k_hw_write_associd(struct ath_hw *ah)
2998 struct ath_common *common = ath9k_hw_common(ah);
3000 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3001 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3008 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3013 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
3015 tsf_lower = REG_READ(ah, AR_TSF_L32);
3016 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
3028 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3030 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3031 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3035 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3037 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3039 ath_dbg(ath9k_hw_common(ah), RESET,
3042 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3046 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3049 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3051 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3055 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
3059 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
3064 REG_WRITE(ah, AR_2040_MODE, macmode);
3098 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3100 return REG_READ(ah, AR_TSF_L32);
3104 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3106 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3109 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3110 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3114 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3120 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3128 !AR_SREV_9300_20_OR_LATER(ah))
3144 ath9k_hw_gen_timer_start_tsf2(ah);
3151 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3156 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3164 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3166 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3168 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3171 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3178 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3181 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3192 REG_SET_BIT(ah, AR_IMR_S5, mask);
3194 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3195 ah->imask |= ATH9K_INT_GENTIMER;
3196 ath9k_hw_set_interrupts(ah);
3201 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3203 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3206 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3209 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3214 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3220 REG_CLR_BIT(ah, AR_IMR_S5,
3227 ah->imask &= ~ATH9K_INT_GENTIMER;
3228 ath9k_hw_set_interrupts(ah);
3233 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3235 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3246 void ath_gen_timer_isr(struct ath_hw *ah)
3248 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3254 trigger_mask = ah->intr_gen_timer_trigger;
3255 thresh_mask = ah->intr_gen_timer_thresh;
3355 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3360 if (AR_SREV_9280_20_OR_LATER(ah)) {
3363 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3364 ah->hw_version.macRev);
3369 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3370 ah->hw_version.macRev,
3371 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3373 ah->hw_version.phyRev);