Lines Matching defs:ah
126 * @ah: atheros hardware structure
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
156 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) ||
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) {
163 if (ah->is_clk_25mhz)
171 } else if (AR_SREV_9340(ah)) {
172 if (ah->is_clk_25mhz) {
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
187 ah->is_clk_25mhz) {
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
209 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
223 ah->curchan = chan;
230 * @ah: atheros hardware structure
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
245 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
253 AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
259 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
269 range = AR_SREV_9462(ah) ? 5 : 10;
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
280 AR_SREV_9550(ah) || AR_SREV_9561(ah))
299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
301 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
303 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
306 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
309 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
319 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
328 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
330 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
332 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
334 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
336 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
338 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
342 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
353 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
357 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
359 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
361 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
380 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
382 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
384 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
386 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
388 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
391 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
392 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
395 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
397 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
399 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
402 if (!AR_SREV_9340(ah) &&
403 REG_READ_FIELD(ah, AR_PHY_MODE,
405 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
416 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
418 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
420 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
424 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
426 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
428 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
430 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
432 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
447 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
452 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
456 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
459 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
461 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
465 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
481 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
490 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
511 ar9003_hw_spur_ofdm(ah,
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
526 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
534 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
544 ar9003_hw_spur_ofdm_clear(ah);
551 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
554 if (AR_SREV_9565(ah) && (i < 4)) {
560 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
568 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
571 if (!AR_SREV_9565(ah))
572 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
573 ar9003_hw_spur_mitigate_ofdm(ah, chan);
576 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
593 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
610 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
617 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
622 if (!AR_SREV_9561(ah))
635 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
642 ath9k_hw_set11nmac2040(ah, chan);
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
650 static void ar9003_hw_init_bb(struct ath_hw *ah,
660 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
664 ath9k_hw_synth_delay(ah, chan, synthDelay);
667 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
669 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
685 static void ar9003_hw_override_ini(struct ath_hw *ah)
694 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
703 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
707 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
709 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
710 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
713 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
715 ah->enabled_cals |= TX_IQ_CAL;
717 ah->enabled_cals &= ~TX_IQ_CAL;
721 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
722 ah->enabled_cals |= TX_CL_CAL;
724 ah->enabled_cals &= ~TX_CL_CAL;
726 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
727 AR_SREV_9561(ah)) {
728 if (ah->is_clk_25mhz) {
729 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1);
730 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
731 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
733 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1);
734 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
735 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
741 static void ar9003_hw_prog_ini(struct ath_hw *ah,
763 REG_WRITE(ah, reg, val);
769 static u32 ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
794 static u32 ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
807 static void ar9003_doubler_fix(struct ath_hw *ah)
809 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
810 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
813 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
816 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
822 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
824 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
826 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
831 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
833 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
835 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
840 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
843 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
846 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
849 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
855 static int ar9003_hw_process_ini(struct ath_hw *ah,
870 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
871 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
872 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
873 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
874 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
875 ar9003_hw_prog_ini(ah,
876 &ah->ini_radio_post_sys2ant,
880 ar9003_doubler_fix(ah);
885 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
887 if (AR_SREV_9462_20_OR_LATER(ah)) {
891 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
892 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
894 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
901 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
902 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
908 if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
909 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
912 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
913 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
918 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
921 if (AR_SREV_9550(ah))
922 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
924 if (AR_SREV_9561(ah))
926 ar9561_hw_get_modes_txgain_index(ah, chan);
928 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
931 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
938 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
939 REG_WRITE_ARRAY(&ah->iniModesFastClock,
945 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
951 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
953 if (AR_SREV_9531(ah))
954 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
958 ah->modes_index = modesIndex;
959 ar9003_hw_override_ini(ah);
960 ar9003_hw_set_channel_regs(ah, chan);
961 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
962 ath9k_hw_apply_txpower(ah, chan, false);
967 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
980 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
984 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
987 REG_WRITE(ah, AR_PHY_MODE, rfMode);
990 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
992 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
995 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1015 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1018 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1021 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1023 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1032 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1036 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1038 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1042 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1044 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1045 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1053 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1055 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1057 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1059 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1062 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1065 struct ath_common *common = ath9k_hw_common(ah);
1066 struct ath9k_channel *chan = ah->curchan;
1067 struct ar5416AniState *aniState = &ah->ani;
1075 switch (cmd & ah->ani_function) {
1086 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1128 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1131 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1142 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1145 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1156 ah->stats.ast_ani_ofdmon++;
1158 ah->stats.ast_ani_ofdmoff++;
1184 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1200 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1221 ah->stats.ast_ani_stepup++;
1223 ah->stats.ast_ani_stepdown++;
1248 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1264 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1285 ah->stats.ast_ani_spurup++;
1287 ah->stats.ast_ani_spurdown++;
1299 if (ah->caps.rx_chainmask == 1)
1302 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1304 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1312 ah->stats.ast_ani_ccklow++;
1314 ah->stats.ast_ani_cckhigh++;
1336 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1348 if (ah->rxchainmask & BIT(i)) {
1349 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1353 if (IS_CHAN_HT40(ah->curchan)) {
1356 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1364 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1366 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1367 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1368 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1369 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1370 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1371 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1373 if (AR_SREV_9330(ah))
1374 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1376 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1377 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1378 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1379 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1380 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1389 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1392 struct ath_common *common = ath9k_hw_common(ah);
1393 struct ath9k_channel *chan = ah->curchan;
1397 aniState = &ah->ani;
1401 ah->hw_version.macVersion,
1402 ah->hw_version.macRev,
1403 ah->opmode,
1406 val = REG_READ(ah, AR_PHY_SFCORR);
1411 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1416 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1421 iniDef->firstep = REG_READ_FIELD(ah,
1424 iniDef->firstepLow = REG_READ_FIELD(ah,
1427 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1430 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1441 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1448 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1459 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1468 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1469 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1471 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1473 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1475 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1476 REG_WRITE_ARRAY(&ah->ini_dfs,
1477 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1481 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1483 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1495 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1500 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1508 if (AR_SREV_9330_11(ah)) {
1512 } else if (AR_SREV_9485(ah)) {
1516 } else if (AR_SREV_9565(ah)) {
1527 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1532 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1549 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1554 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1556 struct ath9k_hw_capabilities *pCap = &ah->caps;
1560 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1563 if (AR_SREV_9485(ah)) {
1564 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1565 IS_CHAN_2GHZ(ah->curchan));
1568 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1570 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1580 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1583 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1585 if (AR_SREV_9485_11_OR_LATER(ah)) {
1589 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1595 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1600 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1606 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1609 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1622 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1624 } else if (AR_SREV_9565(ah)) {
1626 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1628 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1630 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1632 REG_SET_BIT(ah, AR_PHY_RESTART,
1634 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1637 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1639 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1641 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1643 REG_CLR_BIT(ah, AR_PHY_RESTART,
1645 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1648 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1657 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1664 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1676 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1678 if (modesIndex == ah->modes_index) {
1683 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1684 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1685 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1686 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1688 if (AR_SREV_9462_20_OR_LATER(ah))
1689 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1692 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1694 if (AR_SREV_9462_20_OR_LATER(ah)) {
1698 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1699 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1701 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1710 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1711 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1713 if (AR_SREV_9565(ah))
1714 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1720 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1722 ah->modes_index = modesIndex;
1726 ar9003_hw_set_rfmode(ah, chan);
1730 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1736 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1741 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1742 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1755 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1758 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1761 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1763 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1765 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1771 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1773 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1776 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1780 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1782 struct ath_common *common = ath9k_hw_common(ah);
1785 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1793 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1795 REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1796 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1797 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1798 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1799 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1800 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1801 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1802 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1803 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1806 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1808 REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1809 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1812 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1821 ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
1824 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1826 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1827 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1828 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1830 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1834 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1842 ah->tx_power[i] = rate_array[j];
1846 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1855 ah->tx_power[i] = rate_array[j];
1861 ah->tx_power[i] = rate_array[j];
1867 ah->tx_power[i] = rate_array[j];
1872 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1875 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1877 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1879 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1883 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1887 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1890 ar9003_hw_init_txpower_ht(ah, rate_array,
1895 ar9003_hw_init_txpower_stbc(ah,
1901 ar9003_hw_init_txpower_cck(ah, rate_array);
1902 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1905 ar9003_hw_init_txpower_ht(ah, rate_array,
1910 ar9003_hw_init_txpower_stbc(ah,
1918 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1920 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1921 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1934 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1935 AR_SREV_9561(ah))
1967 ar9003_hw_set_nf_limits(ah);
1968 ar9003_hw_set_radar_conf(ah);
1969 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1998 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2002 switch(ah->bb_watchdog_last_status) {
2004 val = REG_READ(ah, AR_PHY_RADAR_0);
2007 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2009 val = REG_READ(ah, AR_PHY_RADAR_0);
2012 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2021 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah))
2035 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2037 struct ath_common *common = ath9k_hw_common(ah);
2038 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2043 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2044 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2049 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2050 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2059 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2060 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2078 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2085 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2094 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2100 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2106 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2107 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2110 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2112 struct ath_common *common = ath9k_hw_common(ah);
2118 status = ah->bb_watchdog_last_status;
2134 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2135 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2137 REG_READ(ah, AR_PHY_GEN_CTRL));
2149 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2159 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2161 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2162 ah->bb_hang_rx_ofdm = true;
2163 val = REG_READ(ah, AR_PHY_RESTART);
2165 REG_WRITE(ah, AR_PHY_RESTART, val);