Lines Matching defs:ah
24 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
26 REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
29 REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
33 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
36 struct ath_common *common = ath9k_hw_common(ah);
39 if (!(REG_READ(ah, address) & bit_position)) {
48 REG_WRITE(ah, address, bit_position);
54 ar9003_mci_reset_req_wakeup(ah);
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG);
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW),
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
79 static void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
83 ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
88 static void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
92 ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
96 static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
98 ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP,
103 static void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
105 ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
109 static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done)
113 ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1,
117 static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done)
119 ar9003_mci_send_message(ah, MCI_SYS_SLEEPING,
124 static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
127 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
136 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
139 static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
142 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
151 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
154 static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
157 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
166 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
170 static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
173 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
191 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
201 static void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
204 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
221 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
224 static void ar9003_mci_prep_interface(struct ath_hw *ah)
226 struct ath_common *common = ath9k_hw_common(ah);
227 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
232 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
236 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW));
240 ar9003_mci_remote_reset(ah, true);
241 ar9003_mci_send_req_wake(ah, true);
243 if (!ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
265 ar9003_mci_send_sys_waking(ah, true);
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
276 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
284 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
286 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI);
289 ar9003_mci_send_lna_transfer(ah, true);
294 if (ar9003_mci_wait_for_interrupt(ah,
308 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
310 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
312 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
314 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
318 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
321 void ar9003_mci_set_full_sleep(struct ath_hw *ah)
323 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
325 if (ar9003_mci_state(ah, MCI_STATE_ENABLE) &&
328 ar9003_mci_send_coex_halt_bt_gpm(ah, true, true);
334 static void ar9003_mci_disable_interrupt(struct ath_hw *ah)
336 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
337 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
340 static void ar9003_mci_enable_interrupt(struct ath_hw *ah)
342 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
343 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
347 static bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
351 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
355 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
358 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
369 void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
371 struct ath_common *common = ath9k_hw_common(ah);
372 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
375 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
376 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
387 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS);
389 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
390 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
394 static void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
396 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
405 static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index)
407 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
425 static void ar9003_mci_observation_set_up(struct ath_hw *ah)
427 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
430 ath9k_hw_gpio_request_out(ah, 3, NULL,
432 ath9k_hw_gpio_request_out(ah, 2, NULL,
434 ath9k_hw_gpio_request_out(ah, 1, NULL,
436 ath9k_hw_gpio_request_out(ah, 0, NULL,
439 ath9k_hw_gpio_request_out(ah, 3, NULL,
441 ath9k_hw_gpio_request_out(ah, 2, NULL,
443 ath9k_hw_gpio_request_out(ah, 1, NULL,
445 ath9k_hw_gpio_request_out(ah, 0, NULL,
447 ath9k_hw_gpio_request_out(ah, 5, NULL,
450 ath9k_hw_gpio_request_out(ah, 3, NULL,
452 ath9k_hw_gpio_request_out(ah, 2, NULL,
454 ath9k_hw_gpio_request_out(ah, 1, NULL,
456 ath9k_hw_gpio_request_out(ah, 0, NULL,
461 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
463 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1);
464 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0);
465 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO);
467 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
468 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
469 REG_WRITE(ah, AR_OBS(ah), 0x4b);
470 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
471 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
472 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
473 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
474 REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS(ah),
478 static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done,
492 return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16,
496 static void ar9003_mci_sync_bt_state(struct ath_hw *ah)
498 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
501 cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP);
508 ar9003_mci_send_coex_version_query(ah, true);
509 ar9003_mci_send_coex_wlan_channels(ah, true);
512 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
516 void ar9003_mci_check_bt(struct ath_hw *ah)
518 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
527 ar9003_mci_sync_bt_state(ah);
528 ar9003_mci_2g5g_switch(ah, true);
536 static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type,
539 struct ath_common *common = ath9k_hw_common(ah);
540 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
549 ar9003_mci_send_coex_version_response(ah, true);
566 ar9003_mci_send_coex_wlan_channels(ah, true);
583 static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
586 struct ath_common *common = ath9k_hw_common(ah);
587 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
602 time_out = ar9003_mci_wait_for_interrupt(ah,
610 offset = ar9003_mci_get_next_gpm_offset(ah, &more_data);
653 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
659 ar9003_mci_process_gpm_extra(ah, recv_type,
673 offset = ar9003_mci_get_next_gpm_offset(ah, &more_data);
682 ar9003_mci_process_gpm_extra(ah, recv_type,
691 bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
693 struct ath_common *common = ath9k_hw_common(ah);
694 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
697 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
709 ar9003_mci_disable_interrupt(ah);
712 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
717 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
726 ar9003_mci_enable_interrupt(ah);
731 int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
734 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
742 if (!ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) &&
743 !ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE))
752 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
756 ar9003_mci_remote_reset(ah, true);
757 ar9003_mci_send_sys_waking(ah, true);
761 ar9003_mci_send_lna_transfer(ah, true);
765 REG_CLR_BIT(ah, AR_PHY_TIMING4,
774 if (!ath9k_hw_init_cal(ah, chan))
777 REG_SET_BIT(ah, AR_PHY_TIMING4,
781 ar9003_mci_enable_interrupt(ah);
785 static void ar9003_mci_mute_bt(struct ath_hw *ah)
787 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
790 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
791 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
792 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
793 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
794 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
795 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
806 ar9003_mci_send_lna_take(ah, true);
810 ar9003_mci_send_sys_sleeping(ah, true);
813 static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable)
815 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
819 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
823 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
824 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
827 if (AR_SREV_9565(ah))
828 REG_RMW_FIELD(ah, AR_MCI_MISC, AR_MCI_MISC_HW_FIX_EN, 1);
832 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
834 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
837 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
840 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
844 static void ar9003_mci_stat_setup(struct ath_hw *ah)
846 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
848 if (!AR_SREV_9565(ah))
852 REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
854 REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
858 REG_RMW_FIELD(ah, AR_MCI_DBG_CNT_CTRL,
863 static void ar9003_mci_set_btcoex_ctrl_9565_1ANT(struct ath_hw *ah)
877 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
879 REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
882 static void ar9003_mci_set_btcoex_ctrl_9565_2ANT(struct ath_hw *ah)
896 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
898 REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
901 static void ar9003_mci_set_btcoex_ctrl_9462(struct ath_hw *ah)
915 REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
918 int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
921 struct ath_common *common = ath9k_hw_common(ah);
922 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
928 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
934 REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
935 REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
936 REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
942 if (AR_SREV_9565(ah)) {
946 ar9003_mci_set_btcoex_ctrl_9565_1ANT(ah);
948 ar9003_mci_set_btcoex_ctrl_9565_2ANT(ah);
950 ar9003_mci_set_btcoex_ctrl_9462(ah);
954 ar9003_mci_osla_setup(ah, true);
956 ar9003_mci_osla_setup(ah, false);
958 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
960 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
963 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
964 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
967 REG_RMW_FIELD(ah, AR_BTCOEX_WL_LNA, AR_BTCOEX_WL_LNA_TIMEOUT, 0x3D090);
971 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
973 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
975 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
978 REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), 0x7f7f7f7f);
982 REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
983 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
986 regval = REG_READ(ah, AR_MCI_COMMAND2);
988 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
993 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
996 ar9003_mci_mute_bt(ah);
1001 ar9003_mci_check_gpm_offset(ah);
1004 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1007 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1010 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET);
1012 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
1017 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
1020 REG_SET_BIT(ah, AR_MCI_TX_CTRL,
1023 ar9003_mci_observation_set_up(ah);
1026 ar9003_mci_prep_interface(ah);
1027 ar9003_mci_stat_setup(ah);
1030 ar9003_mci_enable_interrupt(ah);
1032 if (ath9k_hw_is_aic_enabled(ah))
1033 ar9003_aic_start_normal(ah);
1038 void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
1040 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1042 ar9003_mci_disable_interrupt(ah);
1045 ar9003_mci_mute_bt(ah);
1047 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
1054 static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
1056 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1071 ar9003_mci_send_coex_bt_flags(ah, wait_done,
1075 ar9003_mci_send_coex_bt_flags(ah, wait_done,
1080 static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
1083 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1129 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
1131 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1137 ar9003_mci_send_2g5g_status(ah, true);
1138 ar9003_mci_send_lna_transfer(ah, true);
1141 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
1143 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
1147 ar9003_mci_osla_setup(ah, true);
1149 if (AR_SREV_9462(ah))
1150 REG_WRITE(ah, AR_SELFGEN_MASK, 0x02);
1152 ar9003_mci_send_lna_take(ah, true);
1155 REG_SET_BIT(ah, AR_MCI_TX_CTRL,
1157 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
1160 ar9003_mci_osla_setup(ah, false);
1161 ar9003_mci_send_2g5g_status(ah, true);
1165 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
1169 struct ath_common *common = ath9k_hw_common(ah);
1170 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1176 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
1177 regval = REG_READ(ah, AR_BTCOEX_CTRL);
1182 header, (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0);
1183 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1189 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1194 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
1198 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
1204 REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
1208 REG_WRITE(ah, AR_MCI_COMMAND0,
1215 !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
1217 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1219 ar9003_mci_queue_unsent_gpm(ah, header, payload, false);
1224 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
1230 void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
1232 struct ath_common *common = ath9k_hw_common(ah);
1233 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1243 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1245 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) {
1253 void ar9003_mci_init_cal_done(struct ath_hw *ah)
1255 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1264 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1267 int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
1270 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1277 return ar9003_mci_reset(ah, true, true, true);
1281 void ar9003_mci_cleanup(struct ath_hw *ah)
1284 REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
1285 ar9003_mci_disable_interrupt(ah);
1289 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
1291 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1298 value = REG_READ(ah, AR_BTCOEX_CTRL);
1306 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1314 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1320 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1326 ar9003_mci_send_coex_version_query(ah, true);
1327 ar9003_mci_send_coex_wlan_channels(ah, true);
1330 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
1332 ar9003_mci_2g5g_switch(ah, false);
1335 ar9003_mci_reset_req_wakeup(ah);
1340 if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1343 ar9003_mci_observation_set_up(ah);
1348 ar9003_mci_send_coex_version_response(ah, true);
1351 ar9003_mci_send_coex_version_query(ah, true);
1355 ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
1358 tsf = ath9k_hw_gettsf32(ah);
1360 ath_dbg(ath9k_hw_common(ah), MCI,
1364 ath_dbg(ath9k_hw_common(ah), MCI, "(MCI) RECOVER RX\n");
1366 ar9003_mci_prep_interface(ah);
1369 ar9003_mci_send_coex_wlan_channels(ah, true);
1370 ar9003_mci_2g5g_switch(ah, false);
1380 if (ath9k_hw_is_aic_enabled(ah))
1381 value = ar9003_aic_calibration(ah);
1384 if (ath9k_hw_is_aic_enabled(ah))
1385 ar9003_aic_start_normal(ah);
1388 if (ath9k_hw_is_aic_enabled(ah))
1389 value = ar9003_aic_cal_reset(ah);
1392 if (ath9k_hw_is_aic_enabled(ah))
1393 value = ar9003_aic_calibration_single(ah);
1403 void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
1405 struct ath_common *common = ath9k_hw_common(ah);
1406 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1410 ar9003_mci_send_lna_take(ah, true);
1413 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1416 ar9003_mci_send_2g5g_status(ah, true);
1422 void ar9003_mci_set_power_awake(struct ath_hw *ah)
1429 btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2);
1434 REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23)));
1437 diag_sw = REG_READ(ah, AR_DIAG_SW);
1442 REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));
1443 lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3;
1444 bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP);
1446 REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);
1447 REG_WRITE(ah, AR_DIAG_SW, diag_sw);
1450 REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1);
1451 REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1);
1456 void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
1458 struct ath_common *common = ath9k_hw_common(ah);
1459 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1465 offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1475 u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, u32 *more)
1477 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1489 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1492 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1529 if (ar9003_mci_is_gpm_valid(ah, temp_index)) {
1550 void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor)
1552 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1557 ath_dbg(ath9k_hw_common(ah), MCI, "MCI BT version set: %d.%d\n",
1562 void ar9003_mci_send_wlan_channels(struct ath_hw *ah)
1564 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1567 ar9003_mci_send_coex_wlan_channels(ah, true);
1571 u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
1573 if (!ah->btcoex_hw.mci.concur_tx)