Lines Matching defs:ah
41 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
43 if (AR_SREV_9330_11(ah)) {
45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
67 INIT_INI_ARRAY(&ah->iniModesRxGain,
69 INIT_INI_ARRAY(&ah->iniModesTxGain,
73 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
77 if (ah->is_clk_25mhz)
78 INIT_INI_ARRAY(&ah->iniAdditional,
81 INIT_INI_ARRAY(&ah->iniAdditional,
83 } else if (AR_SREV_9330_12(ah)) {
85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
87 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
93 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
97 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
103 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
107 INIT_INI_ARRAY(&ah->iniModesRxGain,
109 INIT_INI_ARRAY(&ah->iniModesTxGain,
113 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
117 if (ah->is_clk_25mhz)
118 INIT_INI_ARRAY(&ah->iniAdditional,
121 INIT_INI_ARRAY(&ah->iniAdditional,
123 } else if (AR_SREV_9340(ah)) {
125 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
127 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
131 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
133 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
137 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
139 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
143 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
145 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
149 INIT_INI_ARRAY(&ah->iniModesRxGain,
151 INIT_INI_ARRAY(&ah->iniModesTxGain,
154 INIT_INI_ARRAY(&ah->iniModesFastClock,
156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
158 INIT_INI_ARRAY(&ah->ini_dfs,
161 if (!ah->is_clk_25mhz)
162 INIT_INI_ARRAY(&ah->iniAdditional,
164 } else if (AR_SREV_9485_11_OR_LATER(ah)) {
166 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
168 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
172 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
173 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
175 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
179 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
181 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
189 INIT_INI_ARRAY(&ah->iniModesRxGain,
191 INIT_INI_ARRAY(&ah->iniModesTxGain,
195 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
198 if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
199 INIT_INI_ARRAY(&ah->iniPcieSerdes,
201 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
204 INIT_INI_ARRAY(&ah->iniPcieSerdes,
206 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
209 } else if (AR_SREV_9462_21(ah)) {
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
212 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
214 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
216 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
220 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
222 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
224 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
228 INIT_INI_ARRAY(&ah->iniModesRxGain,
230 INIT_INI_ARRAY(&ah->iniModesFastClock,
232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
236 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
237 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
238 INIT_INI_ARRAY(&ah->iniPcieSerdes,
243 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
244 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
245 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
248 } else if (AR_SREV_9462_20(ah)) {
250 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
251 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
254 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
256 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
259 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
261 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
263 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
266 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
268 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
271 INIT_INI_ARRAY(&ah->iniModesRxGain,
275 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
276 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
277 INIT_INI_ARRAY(&ah->iniPcieSerdes,
282 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
283 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
284 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
289 INIT_INI_ARRAY(&ah->iniModesFastClock,
292 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
294 } else if (AR_SREV_9550(ah)) {
296 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
298 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
302 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
304 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
308 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
310 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
314 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
316 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
320 INIT_INI_ARRAY(&ah->iniModesRxGain,
322 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
324 INIT_INI_ARRAY(&ah->iniModesTxGain,
328 INIT_INI_ARRAY(&ah->iniModesFastClock,
330 } else if (AR_SREV_9531(ah)) {
331 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
335 if (AR_SREV_9531_20(ah)) {
336 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
338 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
341 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
346 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
348 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
355 if (AR_SREV_9531_20(ah)) {
356 INIT_INI_ARRAY(&ah->iniModesRxGain,
358 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
361 INIT_INI_ARRAY(&ah->iniModesRxGain,
363 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
367 if (AR_SREV_9531_20(ah))
368 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 else if (AR_SREV_9531_11(ah))
371 INIT_INI_ARRAY(&ah->iniModesTxGain,
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
377 INIT_INI_ARRAY(&ah->iniModesFastClock,
379 } else if (AR_SREV_9561(ah)) {
380 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
382 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
385 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
387 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
390 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
392 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
395 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
397 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
400 INIT_INI_ARRAY(&ah->iniModesRxGain,
402 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
404 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 INIT_INI_ARRAY(&ah->ini_dfs,
409 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
411 INIT_INI_ARRAY(&ah->iniModesFastClock,
413 } else if (AR_SREV_9580(ah)) {
415 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
417 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
421 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
423 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
427 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
429 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
433 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
435 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
439 INIT_INI_ARRAY(&ah->iniModesRxGain,
441 INIT_INI_ARRAY(&ah->iniModesTxGain,
444 INIT_INI_ARRAY(&ah->iniModesFastClock,
446 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
448 INIT_INI_ARRAY(&ah->ini_dfs,
450 } else if (AR_SREV_9565_11_OR_LATER(ah)) {
451 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
453 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
456 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
461 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
466 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
471 INIT_INI_ARRAY(&ah->iniModesRxGain,
473 INIT_INI_ARRAY(&ah->iniModesTxGain,
477 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
478 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
479 INIT_INI_ARRAY(&ah->iniPcieSerdes,
484 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
485 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
486 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
490 INIT_INI_ARRAY(&ah->iniModesFastClock,
492 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
494 } else if (AR_SREV_9565(ah)) {
495 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
497 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
500 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
502 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
505 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
507 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
510 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
512 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
517 INIT_INI_ARRAY(&ah->iniModesTxGain,
521 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
522 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
523 INIT_INI_ARRAY(&ah->iniPcieSerdes,
528 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
529 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
530 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
534 INIT_INI_ARRAY(&ah->iniModesFastClock,
536 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
540 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
542 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
546 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
548 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
552 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
554 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
558 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
560 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
564 INIT_INI_ARRAY(&ah->iniModesRxGain,
566 INIT_INI_ARRAY(&ah->iniModesTxGain,
573 INIT_INI_ARRAY(&ah->iniPcieSerdes,
578 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
582 INIT_INI_ARRAY(&ah->iniModesFastClock,
584 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
586 INIT_INI_ARRAY(&ah->ini_dfs,
591 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
593 if (AR_SREV_9330_12(ah))
594 INIT_INI_ARRAY(&ah->iniModesTxGain,
596 else if (AR_SREV_9330_11(ah))
597 INIT_INI_ARRAY(&ah->iniModesTxGain,
599 else if (AR_SREV_9340(ah))
600 INIT_INI_ARRAY(&ah->iniModesTxGain,
602 else if (AR_SREV_9485_11_OR_LATER(ah))
603 INIT_INI_ARRAY(&ah->iniModesTxGain,
605 else if (AR_SREV_9550(ah))
606 INIT_INI_ARRAY(&ah->iniModesTxGain,
608 else if (AR_SREV_9531_10(ah))
609 INIT_INI_ARRAY(&ah->iniModesTxGain,
611 else if (AR_SREV_9531_11(ah))
612 INIT_INI_ARRAY(&ah->iniModesTxGain,
614 else if (AR_SREV_9531_20(ah))
615 INIT_INI_ARRAY(&ah->iniModesTxGain,
617 else if (AR_SREV_9561(ah))
618 INIT_INI_ARRAY(&ah->iniModesTxGain,
620 else if (AR_SREV_9580(ah))
621 INIT_INI_ARRAY(&ah->iniModesTxGain,
623 else if (AR_SREV_9462_21(ah))
624 INIT_INI_ARRAY(&ah->iniModesTxGain,
626 else if (AR_SREV_9462_20(ah))
627 INIT_INI_ARRAY(&ah->iniModesTxGain,
629 else if (AR_SREV_9565_11(ah))
630 INIT_INI_ARRAY(&ah->iniModesTxGain,
632 else if (AR_SREV_9565(ah))
633 INIT_INI_ARRAY(&ah->iniModesTxGain,
636 INIT_INI_ARRAY(&ah->iniModesTxGain,
640 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
642 if (AR_SREV_9330_12(ah))
643 INIT_INI_ARRAY(&ah->iniModesTxGain,
645 else if (AR_SREV_9330_11(ah))
646 INIT_INI_ARRAY(&ah->iniModesTxGain,
648 else if (AR_SREV_9340(ah))
649 INIT_INI_ARRAY(&ah->iniModesTxGain,
651 else if (AR_SREV_9485_11_OR_LATER(ah))
652 INIT_INI_ARRAY(&ah->iniModesTxGain,
654 else if (AR_SREV_9580(ah))
655 INIT_INI_ARRAY(&ah->iniModesTxGain,
657 else if (AR_SREV_9550(ah))
658 INIT_INI_ARRAY(&ah->iniModesTxGain,
660 else if (AR_SREV_9531(ah)) {
661 if (AR_SREV_9531_20(ah))
662 INIT_INI_ARRAY(&ah->iniModesTxGain,
664 else if (AR_SREV_9531_11(ah))
665 INIT_INI_ARRAY(&ah->iniModesTxGain,
668 INIT_INI_ARRAY(&ah->iniModesTxGain,
670 } else if (AR_SREV_9561(ah))
671 INIT_INI_ARRAY(&ah->iniModesTxGain,
673 else if (AR_SREV_9462_21(ah))
674 INIT_INI_ARRAY(&ah->iniModesTxGain,
676 else if (AR_SREV_9462_20(ah))
677 INIT_INI_ARRAY(&ah->iniModesTxGain,
679 else if (AR_SREV_9565_11(ah))
680 INIT_INI_ARRAY(&ah->iniModesTxGain,
682 else if (AR_SREV_9565(ah))
683 INIT_INI_ARRAY(&ah->iniModesTxGain,
686 INIT_INI_ARRAY(&ah->iniModesTxGain,
690 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
692 if (AR_SREV_9330_12(ah))
693 INIT_INI_ARRAY(&ah->iniModesTxGain,
695 else if (AR_SREV_9330_11(ah))
696 INIT_INI_ARRAY(&ah->iniModesTxGain,
698 else if (AR_SREV_9340(ah))
699 INIT_INI_ARRAY(&ah->iniModesTxGain,
701 else if (AR_SREV_9531_11(ah))
702 INIT_INI_ARRAY(&ah->iniModesTxGain,
704 else if (AR_SREV_9485_11_OR_LATER(ah))
705 INIT_INI_ARRAY(&ah->iniModesTxGain,
707 else if (AR_SREV_9580(ah))
708 INIT_INI_ARRAY(&ah->iniModesTxGain,
710 else if (AR_SREV_9561(ah))
711 INIT_INI_ARRAY(&ah->iniModesTxGain,
713 else if (AR_SREV_9565_11(ah))
714 INIT_INI_ARRAY(&ah->iniModesTxGain,
716 else if (AR_SREV_9565(ah))
717 INIT_INI_ARRAY(&ah->iniModesTxGain,
720 INIT_INI_ARRAY(&ah->iniModesTxGain,
724 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
726 if (AR_SREV_9330_12(ah))
727 INIT_INI_ARRAY(&ah->iniModesTxGain,
729 else if (AR_SREV_9330_11(ah))
730 INIT_INI_ARRAY(&ah->iniModesTxGain,
732 else if (AR_SREV_9340(ah))
733 INIT_INI_ARRAY(&ah->iniModesTxGain,
735 else if (AR_SREV_9485_11_OR_LATER(ah))
736 INIT_INI_ARRAY(&ah->iniModesTxGain,
738 else if (AR_SREV_9580(ah))
739 INIT_INI_ARRAY(&ah->iniModesTxGain,
741 else if (AR_SREV_9565_11(ah))
742 INIT_INI_ARRAY(&ah->iniModesTxGain,
744 else if (AR_SREV_9565(ah))
745 INIT_INI_ARRAY(&ah->iniModesTxGain,
748 if (ah->config.tx_gain_buffalo)
749 INIT_INI_ARRAY(&ah->iniModesTxGain,
752 INIT_INI_ARRAY(&ah->iniModesTxGain,
757 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
759 if (AR_SREV_9340(ah))
760 INIT_INI_ARRAY(&ah->iniModesTxGain,
762 else if (AR_SREV_9580(ah))
763 INIT_INI_ARRAY(&ah->iniModesTxGain,
765 else if (AR_SREV_9462_21(ah))
766 INIT_INI_ARRAY(&ah->iniModesTxGain,
768 else if (AR_SREV_9462_20(ah))
769 INIT_INI_ARRAY(&ah->iniModesTxGain,
772 INIT_INI_ARRAY(&ah->iniModesTxGain,
776 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
778 if (AR_SREV_9485_11_OR_LATER(ah))
779 INIT_INI_ARRAY(&ah->iniModesTxGain,
781 else if (AR_SREV_9580(ah))
782 INIT_INI_ARRAY(&ah->iniModesTxGain,
784 else if (AR_SREV_9561(ah))
785 INIT_INI_ARRAY(&ah->iniModesTxGain,
787 else if (AR_SREV_9300_22(ah))
788 INIT_INI_ARRAY(&ah->iniModesTxGain,
792 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
794 if (AR_SREV_9340(ah))
795 INIT_INI_ARRAY(&ah->iniModesTxGain,
797 else if (AR_SREV_9485_11_OR_LATER(ah))
798 INIT_INI_ARRAY(&ah->iniModesTxGain,
800 else if (AR_SREV_9580(ah))
801 INIT_INI_ARRAY(&ah->iniModesTxGain,
805 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
807 if (AR_SREV_9340(ah))
808 INIT_INI_ARRAY(&ah->iniModesTxGain,
812 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
814 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
826 int idx = ar9003_hw_get_tx_gain_idx(ah);
831 modes[idx](ah);
834 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
836 if (AR_SREV_9330_12(ah))
837 INIT_INI_ARRAY(&ah->iniModesRxGain,
839 else if (AR_SREV_9330_11(ah))
840 INIT_INI_ARRAY(&ah->iniModesRxGain,
842 else if (AR_SREV_9340(ah))
843 INIT_INI_ARRAY(&ah->iniModesRxGain,
845 else if (AR_SREV_9485_11_OR_LATER(ah))
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
848 else if (AR_SREV_9550(ah)) {
849 INIT_INI_ARRAY(&ah->iniModesRxGain,
851 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
853 } else if (AR_SREV_9531(ah)) {
854 INIT_INI_ARRAY(&ah->iniModesRxGain,
856 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
858 } else if (AR_SREV_9561(ah)) {
859 INIT_INI_ARRAY(&ah->iniModesRxGain,
861 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
863 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
865 } else if (AR_SREV_9580(ah))
866 INIT_INI_ARRAY(&ah->iniModesRxGain,
868 else if (AR_SREV_9462_21(ah))
869 INIT_INI_ARRAY(&ah->iniModesRxGain,
871 else if (AR_SREV_9462_20(ah))
872 INIT_INI_ARRAY(&ah->iniModesRxGain,
874 else if (AR_SREV_9565_11(ah))
875 INIT_INI_ARRAY(&ah->iniModesRxGain,
877 else if (AR_SREV_9565(ah))
878 INIT_INI_ARRAY(&ah->iniModesRxGain,
881 INIT_INI_ARRAY(&ah->iniModesRxGain,
885 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
887 if (AR_SREV_9330_12(ah))
888 INIT_INI_ARRAY(&ah->iniModesRxGain,
890 else if (AR_SREV_9330_11(ah))
891 INIT_INI_ARRAY(&ah->iniModesRxGain,
893 else if (AR_SREV_9340(ah))
894 INIT_INI_ARRAY(&ah->iniModesRxGain,
896 else if (AR_SREV_9485_11_OR_LATER(ah))
897 INIT_INI_ARRAY(&ah->iniModesRxGain,
899 else if (AR_SREV_9462_21(ah))
900 INIT_INI_ARRAY(&ah->iniModesRxGain,
902 else if (AR_SREV_9462_20(ah))
903 INIT_INI_ARRAY(&ah->iniModesRxGain,
905 else if (AR_SREV_9550(ah)) {
906 INIT_INI_ARRAY(&ah->iniModesRxGain,
908 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
910 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
911 INIT_INI_ARRAY(&ah->iniModesRxGain,
913 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
915 } else if (AR_SREV_9531_20(ah)) {
916 INIT_INI_ARRAY(&ah->iniModesRxGain,
918 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
920 } else if (AR_SREV_9561(ah)) {
921 INIT_INI_ARRAY(&ah->iniModesRxGain,
923 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
925 } else if (AR_SREV_9580(ah))
926 INIT_INI_ARRAY(&ah->iniModesRxGain,
928 else if (AR_SREV_9565_11(ah))
929 INIT_INI_ARRAY(&ah->iniModesRxGain,
931 else if (AR_SREV_9565(ah))
932 INIT_INI_ARRAY(&ah->iniModesRxGain,
935 INIT_INI_ARRAY(&ah->iniModesRxGain,
939 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
941 if (AR_SREV_9462_21(ah)) {
942 INIT_INI_ARRAY(&ah->iniModesRxGain,
944 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
946 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
948 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
950 } else if (AR_SREV_9462_20(ah)) {
951 INIT_INI_ARRAY(&ah->iniModesRxGain,
953 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
955 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
957 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
962 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
964 if (AR_SREV_9462_21(ah)) {
965 INIT_INI_ARRAY(&ah->iniModesRxGain,
967 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
969 } else if (AR_SREV_9462_20(ah)) {
970 INIT_INI_ARRAY(&ah->iniModesRxGain,
972 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
977 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
979 switch (ar9003_hw_get_rx_gain_idx(ah)) {
982 ar9003_rx_gain_table_mode0(ah);
985 ar9003_rx_gain_table_mode1(ah);
988 ar9003_rx_gain_table_mode2(ah);
991 ar9003_rx_gain_table_mode3(ah);
997 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
999 ar9003_tx_gain_table_apply(ah);
1000 ar9003_rx_gain_table_apply(ah);
1012 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
1023 if (AR_SREV_9462(ah)) {
1024 u32 val = ah->config.aspm_l1_fix;
1028 REG_WRITE(ah, 0x570c, val);
1035 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
1036 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1043 array = power_off ? &ah->iniPcieSerdes :
1044 &ah->iniPcieSerdesLowPower;
1047 REG_WRITE(ah,
1053 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
1058 ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
1059 ah->config.hw_hang_checks |= HW_MAC_HANG;
1064 if (AR_SREV_9300_22(ah))
1065 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
1067 if (AR_SREV_9330(ah))
1068 ah->bb_watchdog_timeout_ms = 85;
1070 ah->bb_watchdog_timeout_ms = 25;
1098 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
1114 dma_dbg_chain = REG_READ(ah, dbg_reg);
1115 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1124 ath_dbg(ath9k_hw_common(ah), RESET,
1130 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1139 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1140 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1141 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1165 if (ath9k_hw_verify_hang(ah, i))
1174 void ar9003_hw_attach_ops(struct ath_hw *ah)
1176 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1177 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1179 ar9003_hw_init_mode_regs(ah);
1181 if (AR_SREV_9003_PCOEM(ah)) {
1182 WARN_ON(!ah->iniPcieSerdes.ia_array);
1183 WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
1192 ar9003_hw_attach_phy_ops(ah);
1193 ar9003_hw_attach_calib_ops(ah);
1194 ar9003_hw_attach_mac_ops(ah);
1195 ar9003_hw_attach_aic_ops(ah);