Lines Matching defs:ah
47 * @ah: atheros hardware structure
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
135 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9,
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
155 ah->curchan = chan;
162 * @ah: atheros hardware structure
168 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
185 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
189 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
215 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
219 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
227 ENABLE_REGWRITE_BUFFER(ah);
233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
240 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
270 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
273 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
275 ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
277 REGWRITE_BUFFER_FLUSH(ah);
280 static void ar9002_olc_init(struct ath_hw *ah)
284 if (!OLC_FOR_AR9280_20_LATER(ah))
287 if (OLC_FOR_AR9287_10_LATER(ah)) {
288 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
290 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
297 ah->originalGain[i] =
298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
300 ah->PDADCdelta = 0;
304 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
311 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
312 if (AR_SREV_9280_20(ah)) {
331 static void ar9002_hw_do_getnf(struct ath_hw *ah,
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
340 if (IS_CHAN_HT40(ah->curchan))
343 if (!(ah->rxchainmask & BIT(1)))
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
349 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
350 if (IS_CHAN_HT40(ah->curchan))
354 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
356 if (AR_SREV_9285(ah)) {
357 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
358 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
359 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
360 } else if (AR_SREV_9287(ah)) {
361 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
362 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
363 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
364 } else if (AR_SREV_9271(ah)) {
365 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
366 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
367 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
369 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
370 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
371 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
372 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
373 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
374 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
378 static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
395 static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
411 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
416 static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
418 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
430 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
432 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);
433 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
445 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
451 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);
452 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);
455 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
467 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
469 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
472 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
477 static void ar9002_hw_spectral_scan_config(struct ath_hw *ah,
484 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
488 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
489 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
491 if (AR_SREV_9280(ah))
497 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
499 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
507 if (AR_SREV_9280(ah))
516 if (AR_SREV_9280(ah)) {
517 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
520 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
522 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
526 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
528 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
534 static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah)
536 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
538 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
542 static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah)
544 struct ath_common *common = ath9k_hw_common(ah);
547 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
555 static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum)
557 REG_SET_BIT(ah, 0x9864, 0x7f000);
558 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
559 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
560 REG_WRITE(ah, AR_CR, AR_CR_RXD);
561 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
562 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);
563 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
564 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);
565 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
566 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
567 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
570 static void ar9002_hw_tx99_stop(struct ath_hw *ah)
572 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
575 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
577 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
578 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
599 ar9002_hw_set_nf_limits(ah);