Lines Matching defs:ah
26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
28 if (AR_SREV_9271(ah)) {
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
35 INIT_INI_ARRAY(&ah->iniPcieSerdes,
38 if (AR_SREV_9287_11_OR_LATER(ah)) {
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
41 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
44 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
45 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
46 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
48 INIT_INI_ARRAY(&ah->iniModesFastClock,
50 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
51 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
52 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
53 if (AR_SREV_9160_11(ah)) {
54 INIT_INI_ARRAY(&ah->iniAddac,
57 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
59 } else if (AR_SREV_9100_OR_LATER(ah)) {
60 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
61 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
62 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
64 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
65 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
66 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
69 if (!AR_SREV_9280_20_OR_LATER(ah)) {
71 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
74 if (!AR_SREV_5416(ah))
75 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
77 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
81 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
82 struct ar5416IniArray *addac = &ah->iniAddac;
86 data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
93 if (!AR_SREV_5416_22_OR_LATER(ah)) {
98 if (AR_SREV_9287_11_OR_LATER(ah)) {
99 INIT_INI_ARRAY(&ah->iniCckfirNormal,
101 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
107 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
111 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_17) {
112 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
115 INIT_INI_ARRAY(&ah->iniModesRxGain,
118 INIT_INI_ARRAY(&ah->iniModesRxGain,
121 INIT_INI_ARRAY(&ah->iniModesRxGain,
124 INIT_INI_ARRAY(&ah->iniModesRxGain,
129 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
131 if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19) {
133 INIT_INI_ARRAY(&ah->iniModesTxGain,
136 INIT_INI_ARRAY(&ah->iniModesTxGain,
139 INIT_INI_ARRAY(&ah->iniModesTxGain,
144 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
147 INIT_INI_ARRAY(&ah->iniModesTxGain,
150 INIT_INI_ARRAY(&ah->iniModesTxGain,
154 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
156 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
158 if (AR_SREV_9287_11_OR_LATER(ah))
159 INIT_INI_ARRAY(&ah->iniModesRxGain,
161 else if (AR_SREV_9280_20(ah))
162 ar9280_20_hw_init_rxgain_ini(ah);
164 if (AR_SREV_9271(ah)) {
165 ar9271_hw_init_txgain_ini(ah, txgain_type);
166 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
167 INIT_INI_ARRAY(&ah->iniModesTxGain,
169 } else if (AR_SREV_9280_20(ah)) {
170 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
171 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
174 if (AR_SREV_9285E_20(ah)) {
175 INIT_INI_ARRAY(&ah->iniModesTxGain,
178 INIT_INI_ARRAY(&ah->iniModesTxGain,
182 if (AR_SREV_9285E_20(ah)) {
183 INIT_INI_ARRAY(&ah->iniModesTxGain,
186 INIT_INI_ARRAY(&ah->iniModesTxGain,
202 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
210 if (AR_SREV_9280_20_OR_LATER(ah)) {
216 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
217 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
218 INI_RA(&ah->iniPcieSerdes, i, 1));
221 ENABLE_REGWRITE_BUFFER(ah);
223 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
224 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
227 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
228 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
229 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
232 * Ignore ah->ah_config.pcie_clock_req setting for
235 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
238 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
242 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
244 REGWRITE_BUFFER_FLUSH(ah);
252 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
254 val = REG_READ(ah, AR_WA(ah));
262 if (ah->config.pcie_waen) {
263 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
266 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {
269 } else if (AR_SREV_9280(ah)) {
275 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
283 if (AR_SREV_9280(ah))
286 if (AR_SREV_9285E_20(ah))
289 REG_WRITE(ah, AR_WA(ah), val);
291 if (ah->config.pcie_waen) {
292 val = ah->config.pcie_waen;
295 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {
298 } else if (AR_SREV_9280(ah)) {
311 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
314 if (AR_SREV_9285E_20(ah))
317 REG_WRITE(ah, AR_WA(ah), val);
320 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
324 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
329 ENABLE_REGWRITE_BUFFER(ah);
331 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
333 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
335 REGWRITE_BUFFER_FLUSH(ah);
337 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
343 int ar9002_hw_rf_claim(struct ath_hw *ah)
347 REG_WRITE(ah, AR_PHY(0), 0x00000007);
349 val = ar9002_hw_get_radiorev(ah);
360 ath_err(ath9k_hw_common(ah),
366 ah->hw_version.analog5GhzRev = val;
371 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
373 if (AR_SREV_9287_13_OR_LATER(ah)) {
374 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
376 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
377 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
379 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
384 static void ar9002_hw_init_hang_checks(struct ath_hw *ah)
386 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
387 ah->config.hw_hang_checks |= HW_BB_RIFS_HANG;
388 ah->config.hw_hang_checks |= HW_BB_DFS_HANG;
391 if (AR_SREV_9280(ah))
392 ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG;
394 if (AR_SREV_5416(ah) || AR_SREV_9100(ah) || AR_SREV_9160(ah))
395 ah->config.hw_hang_checks |= HW_MAC_HANG;
399 int ar9002_hw_attach_ops(struct ath_hw *ah)
401 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
402 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
405 ret = ar9002_hw_init_mode_regs(ah);
414 ret = ar5008_hw_attach_phy_ops(ah);
418 if (AR_SREV_9280_20_OR_LATER(ah))
419 ar9002_hw_attach_phy_ops(ah);
421 ar9002_hw_attach_calib_ops(ah);
422 ar9002_hw_attach_mac_ops(ah);
426 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
436 ENABLE_REGWRITE_BUFFER(ah);
438 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
439 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
440 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
444 val_orig = REG_READ(ah, reg);
448 REG_WRITE(ah, reg, val|val_orig);
450 REG_WRITE(ah, reg, val);
453 REGWRITE_BUFFER_FLUSH(ah);