Lines Matching defs:ah
31 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
36 switch (ah->supp_cals & cal_type) {
50 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
53 struct ath_common *common = ath9k_hw_common(ah);
55 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
61 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
66 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
70 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
79 static bool ar9002_hw_per_calibration(struct ath_hw *ah,
84 struct ath9k_hw_cal_data *caldata = ah->caldata;
88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
91 currCal->calData->calCollect(ah);
92 ah->cal_samples++;
94 if (ah->cal_samples >=
102 currCal->calData->calPostProc(ah, numChains);
107 ar9002_hw_setup_calibration(ah, currCal);
109 } else if (time_after(jiffies, ah->cal_start_time +
111 REG_CLR_BIT(ah, AR_PHY_TIMING_CTRL4(0),
113 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
119 ath9k_hw_reset_calibration(ah, currCal);
125 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
130 ah->totalPowerMeasI[i] +=
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
132 ah->totalPowerMeasQ[i] +=
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
134 ah->totalIqCorrMeas[i] +=
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
136 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
138 ah->cal_samples, i, ah->totalPowerMeasI[i],
139 ah->totalPowerMeasQ[i],
140 ah->totalIqCorrMeas[i]);
144 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
149 ah->totalAdcIOddPhase[i] +=
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
151 ah->totalAdcIEvenPhase[i] +=
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
153 ah->totalAdcQOddPhase[i] +=
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
155 ah->totalAdcQEvenPhase[i] +=
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
158 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
160 ah->cal_samples, i,
161 ah->totalAdcIOddPhase[i],
162 ah->totalAdcIEvenPhase[i],
163 ah->totalAdcQOddPhase[i],
164 ah->totalAdcQEvenPhase[i]);
168 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
173 ah->totalAdcDcOffsetIOddPhase[i] +=
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
175 ah->totalAdcDcOffsetIEvenPhase[i] +=
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
177 ah->totalAdcDcOffsetQOddPhase[i] +=
178 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
179 ah->totalAdcDcOffsetQEvenPhase[i] +=
180 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
182 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
184 ah->cal_samples, i,
185 ah->totalAdcDcOffsetIOddPhase[i],
186 ah->totalAdcDcOffsetIEvenPhase[i],
187 ah->totalAdcDcOffsetQOddPhase[i],
188 ah->totalAdcDcOffsetQEvenPhase[i]);
192 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
194 struct ath_common *common = ath9k_hw_common(ah);
201 powerMeasI = ah->totalPowerMeasI[i];
202 powerMeasQ = ah->totalPowerMeasQ[i];
203 iqCorrMeas = ah->totalIqCorrMeas[i];
211 i, ah->totalIqCorrMeas[i]);
253 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
256 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
265 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
269 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
271 struct ath_common *common = ath9k_hw_common(ah);
276 iOddMeasOffset = ah->totalAdcIOddPhase[i];
277 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
278 qOddMeasOffset = ah->totalAdcQOddPhase[i];
279 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
308 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
319 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
323 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
325 struct ath_common *common = ath9k_hw_common(ah);
329 ah->cal_list_curr->calData;
334 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
335 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
336 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
337 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
363 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
366 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
372 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
373 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
377 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
382 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
385 if (ah->initPDADC == 0 || currPDADC == 0) {
393 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
398 delta = ((currPDADC - ah->initPDADC)*4) / slope;
400 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
402 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
407 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
412 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
415 if (ah->initPDADC == 0 || currPDADC == 0)
418 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
419 delta = (currPDADC - ah->initPDADC + 4) / 8;
421 delta = (currPDADC - ah->initPDADC + 5) / 10;
423 if (delta != ah->PDADCdelta) {
424 ah->PDADCdelta = delta;
426 regval = ah->originalGain[i] - delta;
430 REG_RMW_FIELD(ah,
437 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
452 REG_READ_ARRAY(ah, regList, ARRAY_SIZE(regList));
454 ENABLE_REG_RMW_BUFFER(ah);
456 REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
458 REG_SET_BIT(ah, 0x9808, 1 << 27);
460 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
462 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
464 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
466 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
468 REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
470 REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
472 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
474 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
476 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
478 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
480 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
485 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
487 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
488 REG_RMW_BUFFER_FLUSH(ah);
494 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
496 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
500 regVal = REG_READ(ah, AR9285_AN_RF2G6);
502 REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
504 /* regVal = REG_READ(ah, 0x7834); */
506 regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9),
509 REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
515 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
516 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
517 ah->pacal_info.max_skipcount =
518 2 * ah->pacal_info.max_skipcount;
519 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
521 ah->pacal_info.max_skipcount = 1;
522 ah->pacal_info.skipcount = 0;
523 ah->pacal_info.prev_offset = regVal;
527 ENABLE_REG_RMW_BUFFER(ah);
529 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
531 REG_CLR_BIT(ah, 0x9808, 1 << 27);
532 REG_RMW_BUFFER_FLUSH(ah);
534 ENABLE_REGWRITE_BUFFER(ah);
536 REG_WRITE(ah, regList[i][0], regList[i][1]);
538 REGWRITE_BUFFER_FLUSH(ah);
541 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
543 struct ath_common *common = ath9k_hw_common(ah);
560 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
565 regList[i][1] = REG_READ(ah, regList[i][0]);
567 regVal = REG_READ(ah, 0x7834);
569 REG_WRITE(ah, 0x7834, regVal);
570 regVal = REG_READ(ah, 0x9808);
572 REG_WRITE(ah, 0x9808, regVal);
574 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
575 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
576 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
577 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
578 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
579 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
580 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
581 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
582 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
583 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
584 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
585 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
586 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
587 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
589 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
591 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
592 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
595 regVal = REG_READ(ah, 0x7834);
597 REG_WRITE(ah, 0x7834, regVal);
599 regVal = REG_READ(ah, 0x7834);
601 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
603 REG_WRITE(ah, 0x7834, regVal);
606 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
608 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
609 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
610 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
611 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
618 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
619 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
620 ah->pacal_info.max_skipcount =
621 2 * ah->pacal_info.max_skipcount;
622 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
624 ah->pacal_info.max_skipcount = 1;
625 ah->pacal_info.skipcount = 0;
626 ah->pacal_info.prev_offset = offset;
629 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
630 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
632 regVal = REG_READ(ah, 0x7834);
634 REG_WRITE(ah, 0x7834, regVal);
635 regVal = REG_READ(ah, 0x9808);
637 REG_WRITE(ah, 0x9808, regVal);
640 REG_WRITE(ah, regList[i][0], regList[i][1]);
642 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
645 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
647 if (AR_SREV_9271(ah)) {
648 if (is_reset || !ah->pacal_info.skipcount)
649 ar9271_hw_pa_cal(ah, is_reset);
651 ah->pacal_info.skipcount--;
652 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
653 if (is_reset || !ah->pacal_info.skipcount)
654 ar9285_hw_pa_cal(ah, is_reset);
656 ah->pacal_info.skipcount--;
660 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
662 if (OLC_FOR_AR9287_10_LATER(ah))
663 ar9287_hw_olc_temp_compensation(ah);
664 else if (OLC_FOR_AR9280_20_LATER(ah))
665 ar9280_hw_olc_temp_compensation(ah);
668 static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
671 struct ath9k_cal_list *currCal = ah->cal_list_curr;
675 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF);
676 if (ah->caldata) {
677 nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
679 set_bit(LONGCAL_PENDING, &ah->caldata->cal_flags);
680 else if (test_bit(LONGCAL_PENDING, &ah->caldata->cal_flags))
689 if (!ar9002_hw_per_calibration(ah, chan, rxchainmask, currCal))
693 for (currCal = currCal->calNext; currCal != ah->cal_list_curr;
700 ah->cal_list_curr = currCal;
703 ah->cal_list_curr = ah->cal_list;
709 ath9k_hw_reset_calibration(ah, currCal);
720 if (ath9k_hw_getnf(ah, chan)) {
727 ret = ath9k_hw_loadnf(ah, ah->curchan);
733 if (ah->caldata)
735 &ah->caldata->cal_flags);
736 ath9k_hw_start_nfcal(ah, false);
738 ar9002_hw_pa_cal(ah, false);
739 ar9002_hw_olc_temp_compensation(ah);
747 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
749 struct ath_common *common = ath9k_hw_common(ah);
751 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
753 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
754 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
755 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
757 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
758 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);
759 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah),
766 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
767 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
768 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
770 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
771 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);
772 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
773 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);
774 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL,
782 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
783 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
784 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);
789 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
801 if (!(ar9285_hw_cl_cal(ah, chan)))
804 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
808 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
817 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
819 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
829 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
830 if (AR_SREV_9285E_20(ah)) {
831 REG_WRITE(ah, AR9285_RF2G5,
835 REG_WRITE(ah, AR9285_RF2G5,
839 retv = ar9285_hw_cl_cal(ah, chan);
840 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
845 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
847 struct ath_common *common = ath9k_hw_common(ah);
849 if (AR_SREV_9271(ah)) {
850 if (!ar9285_hw_cl_cal(ah, chan))
852 } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
853 if (!ar9285_hw_clc(ah, chan))
856 if (AR_SREV_9280_20_OR_LATER(ah)) {
857 if (!AR_SREV_9287_11_OR_LATER(ah))
858 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
865 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
866 REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) |
870 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah),
879 if (AR_SREV_9280_20_OR_LATER(ah)) {
880 if (!AR_SREV_9287_11_OR_LATER(ah))
881 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
883 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
889 ar9002_hw_pa_cal(ah, true);
890 ath9k_hw_loadnf(ah, chan);
891 ath9k_hw_start_nfcal(ah, true);
893 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
896 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
897 ah->supp_cals = IQ_MISMATCH_CAL;
899 if (AR_SREV_9160_10_OR_LATER(ah))
900 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
902 if (AR_SREV_9287(ah))
903 ah->supp_cals &= ~ADC_GAIN_CAL;
905 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
906 INIT_CAL(&ah->adcgain_caldata);
907 INSERT_CAL(ah, &ah->adcgain_caldata);
912 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
913 INIT_CAL(&ah->adcdc_caldata);
914 INSERT_CAL(ah, &ah->adcdc_caldata);
919 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
920 INIT_CAL(&ah->iq_caldata);
921 INSERT_CAL(ah, &ah->iq_caldata);
925 ah->cal_list_curr = ah->cal_list;
927 if (ah->cal_list_curr)
928 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
931 if (ah->caldata)
932 ah->caldata->CalValid = 0;
980 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
982 if (AR_SREV_9100(ah)) {
983 ah->iq_caldata.calData = &iq_cal_multi_sample;
984 ah->supp_cals = IQ_MISMATCH_CAL;
988 if (AR_SREV_9160_10_OR_LATER(ah)) {
989 if (AR_SREV_9280_20_OR_LATER(ah)) {
990 ah->iq_caldata.calData = &iq_cal_single_sample;
991 ah->adcgain_caldata.calData =
993 ah->adcdc_caldata.calData =
996 ah->iq_caldata.calData = &iq_cal_multi_sample;
997 ah->adcgain_caldata.calData =
999 ah->adcdc_caldata.calData =
1002 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
1004 if (AR_SREV_9287(ah))
1005 ah->supp_cals &= ~ADC_GAIN_CAL;
1009 void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
1011 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1012 struct ath_hw_ops *ops = ath9k_hw_ops(ah);