Lines Matching defs:ah
89 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
91 struct ar5416IniArray *array = &ah->iniBank6;
92 u32 *data = ah->analogBank6Data;
95 ENABLE_REGWRITE_BUFFER(ah);
98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
102 REGWRITE_BUFFER_FLUSH(ah);
164 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
166 struct ath_common *common = ath9k_hw_common(ah);
171 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
174 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
190 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
193 ar5008_write_bank6(ah, ®_writes);
201 * cache in ah->analogBank6Data.
203 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
205 struct ath_common *common = ath9k_hw_common(ah);
213 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
233 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
250 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
262 ar5008_hw_force_bias(ah, freq);
268 REG_WRITE(ah, AR_PHY(0x37), reg32);
270 ah->curchan = chan;
275 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
367 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
368 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
378 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
379 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
390 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
401 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
412 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
422 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
423 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
432 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
447 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
468 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
475 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
486 REG_WRITE(ah, AR_PHY_TIMING11, new);
488 ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
493 * @ah: atheros hardware structure
497 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
499 int size = ah->iniBank6.ia_rows * sizeof(u32);
501 if (AR_SREV_9280_20_OR_LATER(ah))
504 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
505 if (!ah->analogBank6Data)
514 * @ah: atheros hardware structure
524 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
539 if (AR_SREV_9280_20_OR_LATER(ah))
543 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah);
545 for (i = 0; i < ah->iniBank6.ia_rows; i++)
546 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
551 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
552 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
553 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
555 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
558 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
559 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
560 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
562 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
572 ar5008_write_bank6(ah, ®Writes);
578 static void ar5008_hw_init_bb(struct ath_hw *ah,
583 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
585 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
587 ath9k_hw_synth_delay(ah, chan, synthDelay);
590 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
594 rx_chainmask = ah->rxchainmask;
595 tx_chainmask = ah->txchainmask;
600 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
604 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
605 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
606 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
613 ENABLE_REGWRITE_BUFFER(ah);
614 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
615 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
618 ENABLE_REGWRITE_BUFFER(ah);
622 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
624 REGWRITE_BUFFER_FLUSH(ah);
627 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
630 if (AR_SREV_9100(ah))
631 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
632 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
635 static void ar5008_hw_override_ini(struct ath_hw *ah,
645 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
647 if (AR_SREV_9280_20_OR_LATER(ah)) {
655 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
658 if (!AR_SREV_9271(ah))
661 if (AR_SREV_9287_11_OR_LATER(ah))
666 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
669 if (AR_SREV_9280_20_OR_LATER(ah))
675 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
681 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
682 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
684 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
688 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
694 if (AR_SREV_9285_12_OR_LATER(ah))
695 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
708 ENABLE_REGWRITE_BUFFER(ah);
709 REG_WRITE(ah, AR_PHY_TURBO, phymode);
713 ath9k_hw_set11nmac2040(ah, chan);
715 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
716 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
718 REGWRITE_BUFFER_FLUSH(ah);
722 static int ar5008_hw_process_ini(struct ath_hw *ah,
725 struct ath_common *common = ath9k_hw_common(ah);
741 REG_WRITE(ah, AR_PHY(0), 0x00000007);
744 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
745 if (ah->eep_ops->set_addac)
746 ah->eep_ops->set_addac(ah, chan);
748 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
749 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
751 ENABLE_REGWRITE_BUFFER(ah);
753 for (i = 0; i < ah->iniModes.ia_rows; i++) {
754 u32 reg = INI_RA(&ah->iniModes, i, 0);
755 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
757 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
760 REG_WRITE(ah, reg, val);
763 && ah->config.analog_shiftreg
771 REGWRITE_BUFFER_FLUSH(ah);
773 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
774 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
776 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
777 AR_SREV_9287_11_OR_LATER(ah))
778 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
780 if (AR_SREV_9271_10(ah)) {
781 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
782 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
785 ENABLE_REGWRITE_BUFFER(ah);
788 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
789 u32 reg = INI_RA(&ah->iniCommon, i, 0);
790 u32 val = INI_RA(&ah->iniCommon, i, 1);
792 REG_WRITE(ah, reg, val);
795 && ah->config.analog_shiftreg
803 REGWRITE_BUFFER_FLUSH(ah);
805 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
807 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
808 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
811 ar5008_hw_override_ini(ah, chan);
812 ar5008_hw_set_channel_regs(ah, chan);
813 ar5008_hw_init_chain_masks(ah);
814 ath9k_olc_init(ah);
815 ath9k_hw_apply_txpower(ah, chan, false);
818 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
819 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
826 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
838 if (!AR_SREV_9280_20_OR_LATER(ah))
842 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
845 REG_WRITE(ah, AR_PHY_MODE, rfMode);
848 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
850 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
853 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
865 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
868 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
871 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
873 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
878 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
881 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
883 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
887 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
889 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
890 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
894 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
903 static void ar5008_restore_chainmask(struct ath_hw *ah)
905 int rx_chainmask = ah->rxchainmask;
908 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
909 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
913 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
933 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
953 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
957 struct ath_common *common = ath9k_hw_common(ah);
958 struct ath9k_channel *chan = ah->curchan;
959 struct ar5416AniState *aniState = &ah->ani;
962 switch (cmd & ah->ani_function) {
997 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1003 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1005 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1007 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1009 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1013 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1015 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1017 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1019 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1023 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1026 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1037 ah->stats.ast_ani_ofdmon++;
1039 ah->stats.ast_ani_ofdmoff++;
1048 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1050 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1071 ah->stats.ast_ani_stepup++;
1073 ah->stats.ast_ani_stepdown++;
1082 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1085 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1106 ah->stats.ast_ani_spurup++;
1108 ah->stats.ast_ani_spurdown++;
1137 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1148 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1151 if (!IS_CHAN_HT40(ah->curchan))
1154 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1157 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1160 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1169 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 struct ath9k_channel *chan = ah->curchan;
1173 struct ar5416AniState *aniState = &ah->ani;
1180 ah->hw_version.macVersion,
1181 ah->hw_version.macRev,
1182 ah->opmode,
1185 val = REG_READ(ah, AR_PHY_SFCORR);
1190 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1195 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1200 iniDef->firstep = REG_READ_FIELD(ah,
1203 iniDef->firstepLow = REG_READ_FIELD(ah,
1206 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1209 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1220 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1222 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1223 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1224 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1225 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1226 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1227 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1230 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1236 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1247 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1256 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1257 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1259 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1261 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1264 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1266 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1278 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array)
1281 ah->tx_power[0] = CCK_DELTA(ah, rate_array[rate1l]);
1282 ah->tx_power[1] = CCK_DELTA(ah, min(rate_array[rate2l],
1284 ah->tx_power[2] = CCK_DELTA(ah, min(rate_array[rate5_5l],
1286 ah->tx_power[3] = CCK_DELTA(ah, min(rate_array[rate11l],
1291 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array,
1297 ah->tx_power[i] = rate_array[idx];
1302 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array,
1309 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta;
1312 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset],
1316 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1320 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1323 ar5008_hw_init_txpower_ht(ah, rate_array,
1330 ar5008_hw_init_txpower_cck(ah, rate_array);
1331 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1334 ar5008_hw_init_txpower_ht(ah, rate_array,
1343 int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1345 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1356 ret = ar5008_hw_rf_alloc_ext_banks(ah);
1379 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1384 ar5008_hw_set_nf_limits(ah);
1385 ar5008_hw_set_radar_conf(ah);
1386 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));