Lines Matching defs:ah
53 * @ah: The &struct ath5k_hw
67 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
74 data = ath5k_hw_reg_read(ah, reg);
92 * @ah: The &struct ath5k_hw
101 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
103 struct ath_common *common = ath5k_hw_common(ah);
109 * @ah: The &struct ath5k_hw
118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
120 struct ath_common *common = ath5k_hw_common(ah);
126 * @ah: The &struct ath5k_hw
132 ath5k_hw_init_core_clock(struct ath5k_hw *ah)
134 struct ieee80211_channel *channel = ah->ah_current_channel;
135 struct ath_common *common = ath5k_hw_common(ah);
156 switch (ah->ah_bwmode) {
180 if (ah->ah_version != AR5K_AR5210)
181 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
186 if ((ah->ah_radio == AR5K_RF5112) ||
187 (ah->ah_radio == AR5K_RF2413) ||
188 (ah->ah_radio == AR5K_RF5413) ||
189 (ah->ah_radio == AR5K_RF2316) ||
190 (ah->ah_radio == AR5K_RF2317))
200 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
214 if (ah->ah_version == AR5K_AR5210) {
220 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
231 switch (ah->ah_bwmode) {
257 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
260 if (ah->ah_radio == AR5K_RF5112) {
261 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
269 * @ah: The &struct ath5k_hw
281 ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
283 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
293 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
295 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
299 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
301 if ((ah->ah_radio == AR5K_RF5112) ||
302 (ah->ah_radio == AR5K_RF5413) ||
303 (ah->ah_radio == AR5K_RF2316) ||
304 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
308 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
310 if ((ah->ah_radio == AR5K_RF5112) ||
311 (ah->ah_radio == AR5K_RF5413) ||
312 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
314 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
315 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
316 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
317 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
321 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
322 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
323 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
324 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
329 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
336 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
339 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
343 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
346 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
352 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
354 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
355 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
357 if ((ah->ah_radio == AR5K_RF5112) ||
358 (ah->ah_radio == AR5K_RF5413) ||
359 (ah->ah_radio == AR5K_RF2316) ||
360 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
364 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
367 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
369 if ((ah->ah_radio == AR5K_RF5112) ||
370 (ah->ah_radio == AR5K_RF5413) ||
371 (ah->ah_radio == AR5K_RF2316) ||
372 (ah->ah_radio == AR5K_RF2317))
376 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
387 * @ah: The &struct ath5k_hw
397 ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
403 ath5k_hw_reg_read(ah, AR5K_RXDP);
408 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
413 if (ah->ah_version == AR5K_AR5210) {
423 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
431 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
438 * @ah: The &struct ath5k_hw
446 ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
453 /* ah->ah_mac_srev is not available at this point yet */
454 if (ah->devid >= AR5K_SREV_AR2315_R6) {
462 if (to_platform_device(ah->dev)->id == 0) {
493 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
500 * @ah: The &struct ath5k_hw
514 ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
520 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
528 ath5k_hw_reg_write(ah,
538 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
551 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
562 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
568 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
574 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
589 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
596 * @ah: The &struct ath5k_hw
607 ath5k_hw_on_hold(struct ath5k_hw *ah)
609 struct pci_dev *pdev = ah->pdev;
613 if (ath5k_get_bus_type(ah) == ATH_AHB)
617 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
619 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
633 if (ah->ah_version == AR5K_AR5210) {
634 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
639 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
644 ATH5K_ERR(ah, "failed to put device on warm reset\n");
649 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
651 ATH5K_ERR(ah, "failed to put device on hold\n");
660 * @ah: The &struct ath5k_hw
669 ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
671 struct pci_dev *pdev = ah->pdev;
679 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
681 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
683 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
698 if (ah->ah_version == AR5K_AR5210) {
699 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
704 if (ath5k_get_bus_type(ah) == ATH_AHB)
705 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
708 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
713 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
718 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
720 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
727 if (ath5k_get_bus_type(ah) == ATH_AHB)
728 ret = ath5k_hw_wisoc_reset(ah, 0);
730 ret = ath5k_hw_nic_reset(ah, 0);
733 ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
742 if (ah->ah_version != AR5K_AR5210) {
747 if (ah->ah_radio >= AR5K_RF5112) {
769 if (ah->ah_version == AR5K_AR5211)
779 if (ah->ah_radio == AR5K_RF5413)
784 ATH5K_ERR(ah, "invalid radio frequency mode\n");
791 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
793 if (ah->ah_radio != AR5K_RF2425)
795 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
796 if (ah->ah_radio == AR5K_RF5413) {
797 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
800 } else if (ah->ah_version == AR5K_AR5212) {
801 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
810 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
811 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
815 if (ah->ah_version != AR5K_AR5210) {
818 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
819 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
824 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
825 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
838 * @ah: The &struct ath5k_hw
848 ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
851 if (ah->ah_version == AR5K_AR5212 &&
852 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
855 ath5k_hw_reg_write(ah,
867 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
870 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
874 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
878 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
879 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
882 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
883 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
887 if ((ah->ah_radio == AR5K_RF5413) ||
888 (ah->ah_radio == AR5K_RF2317) ||
889 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
897 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
898 ath5k_hw_reg_write(ah, fast_adc,
903 if (ah->ah_radio == AR5K_RF5112 &&
904 ah->ah_radio_5ghz_revision <
907 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
913 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
916 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
918 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
920 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
923 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
927 if (ah->ah_bwmode) {
931 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
933 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
940 if (ah->ah_version == AR5K_AR5212)
941 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
945 if (ah->ah_version == AR5K_AR5210) {
947 ath5k_hw_reg_write(ah,
954 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
955 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
956 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
960 } else if (ah->ah_version == AR5K_AR5210) {
962 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
969 * @ah: The &struct ath5k_hw
976 ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
979 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
984 if (ah->ah_version == AR5K_AR5210)
987 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);
1000 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
1002 ath5k_hw_reg_write(ah,
1009 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
1013 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
1014 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
1020 ath5k_hw_set_antenna_switch(ah, ee_mode);
1023 ath5k_hw_reg_write(ah,
1027 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
1028 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
1030 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1035 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1040 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1044 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1049 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1055 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1060 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1065 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1069 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1074 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1075 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1081 ath5k_hw_reg_write(ah,
1088 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
1093 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
1100 if (ath5k_hw_chan_has_spur_noise(ah, channel))
1101 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1106 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1112 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1115 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1117 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1121 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1122 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1132 * @ah: The &struct ath5k_hw
1146 ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1162 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1163 (ah->ah_radio != AR5K_RF5413))
1169 if (ah->ah_version == AR5K_AR5212)
1170 ath5k_hw_set_sleep_clock(ah, false);
1177 if (ah->ah_version <= AR5K_AR5211) {
1178 ATH5K_ERR(ah,
1184 if (ah->ah_version < AR5K_AR5211) {
1185 ATH5K_ERR(ah,
1191 ATH5K_ERR(ah,
1201 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1203 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1209 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1218 if (ah->ah_version != AR5K_AR5210) {
1224 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1227 s_seq[i] = ath5k_hw_reg_read(ah,
1231 s_seq[0] = ath5k_hw_reg_read(ah,
1248 if (ah->ah_version == AR5K_AR5211) {
1249 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1250 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1256 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1258 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1259 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1267 if (ah->ah_version == AR5K_AR5212 &&
1268 (ah->ah_radio <= AR5K_RF5112)) {
1269 if (!fast && ah->ah_rf_banks != NULL)
1270 ath5k_hw_gainf_calibrate(ah);
1274 ret = ath5k_hw_nic_wakeup(ah, channel);
1279 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1280 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1282 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1286 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1291 ath5k_hw_init_core_clock(ah);
1298 ath5k_hw_tweak_initval_settings(ah, channel);
1301 ath5k_hw_commit_eeprom_settings(ah, channel);
1309 if (ah->ah_version != AR5K_AR5210) {
1310 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1312 ath5k_hw_reg_write(ah, s_seq[i],
1315 ath5k_hw_reg_write(ah, s_seq[0],
1319 if (ah->ah_version == AR5K_AR5211) {
1320 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1321 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1326 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1329 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1330 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1335 ath5k_hw_pcu_init(ah, op_mode);
1340 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1342 ATH5K_ERR(ah,
1350 ret = ath5k_hw_init_queues(ah);
1358 ath5k_hw_dma_init(ah);
1370 if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1372 ath5k_hw_set_sleep_clock(ah, true);
1377 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1378 ath5k_hw_reset_tsf(ah);