Lines Matching defs:ah
79 * ah->ah_ack_bitrate_high to true else base rate is
103 * @ah: The &struct ath5k_hw
114 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,
122 if (!ah->ah_bwmode) {
123 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,
139 switch (ah->ah_bwmode) {
173 * @ah: The &struct ath5k_hw
176 ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
178 struct ieee80211_channel *channel = ah->ah_current_channel;
181 switch (ah->ah_bwmode) {
194 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot)
204 * @ah: The &struct ath5k_hw
207 ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
209 struct ieee80211_channel *channel = ah->ah_current_channel;
212 switch (ah->ah_bwmode) {
235 * @ah: The &struct ath5k_hw
244 ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
246 struct ath5k_statistics *stats = &ah->stats;
249 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
250 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
251 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
252 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
253 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
263 * @ah: The &struct ath5k_hw
278 ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
286 for (i = 0; i < ah->sbands[band].n_bitrates; i++) {
290 if (ah->ah_ack_bitrate_high)
291 rate = &ah->sbands[band].bitrates[ack_rates_high[i]];
294 rate = &ah->sbands[band].bitrates[0];
297 rate = &ah->sbands[band].bitrates[4];
308 tx_time = ath5k_hw_get_frame_duration(ah, band, 10,
311 ath5k_hw_reg_write(ah, tx_time, reg);
316 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true);
317 ath5k_hw_reg_write(ah, tx_time,
324 * @ah: The &struct ath5k_hw
328 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
330 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
334 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
335 ath5k_hw_htoclock(ah, timeout));
342 * @ah: The &struct ath5k_hw
346 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
348 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
352 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
353 ath5k_hw_htoclock(ah, timeout));
365 * @ah: The &struct ath5k_hw
371 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
373 struct ath_common *common = ath5k_hw_common(ah);
380 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
385 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
386 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
393 * @ah: The &struct ath5k_hw
399 ath5k_hw_set_bssid(struct ath5k_hw *ah)
401 struct ath_common *common = ath5k_hw_common(ah);
407 if (ah->ah_version == AR5K_AR5212)
413 ath5k_hw_reg_write(ah,
416 ath5k_hw_reg_write(ah,
422 ath5k_hw_disable_pspoll(ah);
426 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
429 ath5k_hw_enable_pspoll(ah, NULL, 0);
434 * @ah: The &struct ath5k_hw
448 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
450 struct ath_common *common = ath5k_hw_common(ah);
455 if (ah->ah_version == AR5K_AR5212)
461 * @ah: The &struct ath5k_hw
466 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
468 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
469 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
474 * @ah: The &struct ath5k_hw
483 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
487 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
490 if (ah->ah_version == AR5K_AR5212) {
491 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
504 * @ah: The &struct ath5k_hw
512 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
517 if (ah->ah_version == AR5K_AR5212) {
527 if (ah->ah_version == AR5K_AR5210 &&
535 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
537 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
540 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
543 if (ah->ah_version == AR5K_AR5212)
544 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
557 * @ah: The &struct ath5k_hw
562 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
583 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
585 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
586 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
603 * @ah: The &struct ath5k_hw
609 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
611 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
612 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
617 * @ah: The &struct ath5k_hw
622 ath5k_hw_reset_tsf(struct ath5k_hw *ah)
626 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
634 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
635 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
640 * @ah: The &struct ath5k_hw
648 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
655 switch (ah->opmode) {
662 if (ah->ah_version == AR5K_AR5210) {
670 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
673 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
693 if (ah->opmode == NL80211_IFTYPE_AP ||
694 ah->opmode == NL80211_IFTYPE_MESH_POINT)
695 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
697 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
698 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
699 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
700 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
704 ath5k_hw_reset_tsf(ah);
706 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
715 if (ah->ah_version == AR5K_AR5210)
716 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
718 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
723 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
759 * @ah: The &struct ath5k_hw
797 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
801 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
802 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
803 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
818 * @ah: The &struct ath5k_hw
824 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
827 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
828 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
831 ath5k_hw_set_ifs_intervals(ah, slot_time);
832 ath5k_hw_set_ack_timeout(ah, ack_timeout);
833 ath5k_hw_set_cts_timeout(ah, cts_timeout);
835 ah->ah_coverage_class = coverage_class;
844 * @ah: The &struct ath5k_hw
852 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
854 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
859 * @ah: The &struct ath5k_hw
864 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
866 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
871 * @ah: The &struct ath5k_hw
877 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
879 struct ath_common *common = ath5k_hw_common(ah);
882 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
885 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
888 | (ah->ah_version == AR5K_AR5210 ?
897 if (ah->ah_version == AR5K_AR5210)
900 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
907 if (ah->ah_version == AR5K_AR5210)
910 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
915 | (ah->ah_version == AR5K_AR5210 ?
920 | (ah->ah_version == AR5K_AR5210 ?
933 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
934 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
939 if (ah->ah_version == AR5K_AR5210)
940 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
947 * @ah: The &struct ath5k_hw
954 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
957 ath5k_hw_set_bssid(ah);
960 ath5k_hw_set_opmode(ah, op_mode);
966 if (ah->ah_version == AR5K_AR5212 &&
967 ah->nvifs)
968 ath5k_hw_write_rate_duration(ah);
978 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
984 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
985 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
986 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
990 if (ah->ah_version == AR5K_AR5212) {
991 ath5k_hw_reg_write(ah,
999 if (ah->ah_coverage_class > 0)
1000 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1003 if (ah->ah_version == AR5K_AR5212) {
1005 if (ah->ah_ack_bitrate_high)
1006 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
1008 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);