ath/ath5k/eeprom.c

41 							unsigned int mode)
48 	if (mode == AR5K_EEPROM_MODE_11A) {
190 		unsigned int mode)
198 	ee->ee_switch_settling[mode]	= (val >> 8) & 0x7f;
199 	ee->ee_atn_tx_rx[mode]		= (val >> 2) & 0x3f;
200 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
203 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
204 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
205 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
208 	ee->ee_ant_control[mode][i++]	= (val >> 10) & 0x3f;
209 	ee->ee_ant_control[mode][i++]	= (val >> 4) & 0x3f;
210 	ee->ee_ant_control[mode][i]	= (val << 2) & 0x3f;
213 	ee->ee_ant_control[mode][i++]	|= (val >> 14) & 0x3;
214 	ee->ee_ant_control[mode][i++]	= (val >> 8) & 0x3f;
215 	ee->ee_ant_control[mode][i++]	= (val >> 2) & 0x3f;
216 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
219 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
220 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
221 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
224 	ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
225 	    (ee->ee_ant_control[mode][0] << 4);
226 	ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
227 	     ee->ee_ant_control[mode][1]	|
228 	    (ee->ee_ant_control[mode][2] << 6)	|
229 	    (ee->ee_ant_control[mode][3] << 12) |
230 	    (ee->ee_ant_control[mode][4] << 18) |
231 	    (ee->ee_ant_control[mode][5] << 24);
232 	ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
233 	     ee->ee_ant_control[mode][6]	|
234 	    (ee->ee_ant_control[mode][7] << 6)	|
235 	    (ee->ee_ant_control[mode][8] << 12) |
236 	    (ee->ee_ant_control[mode][9] << 18) |
237 	    (ee->ee_ant_control[mode][10] << 24);
246  * Read supported modes and some mode-specific calibration data
250 		unsigned int mode)
256 	ee->ee_n_piers[mode] = 0;
258 	ee->ee_adc_desired_size[mode]	= (s8)((val >> 8) & 0xff);
259 	switch (mode) {
261 		ee->ee_ob[mode][3]	= (val >> 5) & 0x7;
262 		ee->ee_db[mode][3]	= (val >> 2) & 0x7;
263 		ee->ee_ob[mode][2]	= (val << 1) & 0x7;
266 		ee->ee_ob[mode][2]	|= (val >> 15) & 0x1;
267 		ee->ee_db[mode][2]	= (val >> 12) & 0x7;
268 		ee->ee_ob[mode][1]	= (val >> 9) & 0x7;
269 		ee->ee_db[mode][1]	= (val >> 6) & 0x7;
270 		ee->ee_ob[mode][0]	= (val >> 3) & 0x7;
271 		ee->ee_db[mode][0]	= val & 0x7;
275 		ee->ee_ob[mode][1]	= (val >> 4) & 0x7;
276 		ee->ee_db[mode][1]	= val & 0x7;
281 	ee->ee_tx_end2xlna_enable[mode]	= (val >> 8) & 0xff;
282 	ee->ee_thr_62[mode]		= val & 0xff;
285 		ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
288 	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
289 	ee->ee_tx_frm2xpa_enable[mode]	= val & 0xff;
292 	ee->ee_pga_desired_size[mode]	= (val >> 8) & 0xff;
295 		ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
297 		ee->ee_noise_floor_thr[mode] = val & 0xff;
300 		ee->ee_noise_floor_thr[mode] =
301 		    mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
304 	ee->ee_xlna_gain[mode]		= (val >> 5) & 0xff;
305 	ee->ee_x_gain[mode]		= (val >> 1) & 0xf;
306 	ee->ee_xpd[mode]		= val & 0x1;
309 	    mode != AR5K_EEPROM_MODE_11B)
310 		ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
314 		ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
316 		if (mode == AR5K_EEPROM_MODE_11A)
317 			ee->ee_xr_power[mode] = val & 0x3f;
320 			ee->ee_ob[mode][0] = val & 0x7;
321 			ee->ee_db[mode][0] = (val >> 3) & 0x7;
326 		ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
329 		ee->ee_i_gain[mode] = (val >> 13) & 0x7;
332 		ee->ee_i_gain[mode] |= (val << 3) & 0x38;
334 		if (mode == AR5K_EEPROM_MODE_11G) {
342 			mode == AR5K_EEPROM_MODE_11A) {
343 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
344 		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
353 	switch (mode) {
359 		ee->ee_margin_tx_rx[mode] = val & 0x3f;
365 			ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
367 			ee->ee_n_piers[mode]++;
370 			ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
372 			ee->ee_n_piers[mode]++;
376 			ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
378 			ee->ee_n_piers[mode]++;
381 			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
387 			ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
389 			ee->ee_n_piers[mode]++;
392 			ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
394 			ee->ee_n_piers[mode]++;
397 		ee->ee_turbo_max_power[mode] = val & 0x7f;
398 		ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
402 			ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
404 			ee->ee_n_piers[mode]++;
407 			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
410 		ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
411 		ee->ee_q_cal[mode] = val & 0x1f;
421 	 * Read turbo mode information on newer EEPROM versions
426 	switch (mode) {
428 		ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
430 		ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
432 		ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
433 		ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
435 		ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
437 		ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
438 		ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
444 		ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
446 		ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
448 		ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
449 		ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
451 		ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
453 		ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
454 		ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
465 /* Read mode-specific data (except power calibration data) */
471 	unsigned int mode;
485 	for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
486 		offset = mode_offset[mode];
488 		ret = ath5k_eeprom_read_ants(ah, &offset, mode);
492 		ret = ath5k_eeprom_read_modes(ah, &offset, mode);
507 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
511 			struct ath5k_chan_pcal_info *pc, unsigned int mode)
519 	ee->ee_n_piers[mode] = 0;
528 				freq1, mode);
529 		ee->ee_n_piers[mode]++;
536 				freq2, mode);
537 		ee->ee_n_piers[mode]++;
601 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
606 	switch (mode) {
619 		mode);
667 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
673 	switch (mode) {
693 	for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
714 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
721 	u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
724 	for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
743 			if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
752 		ee->ee_pd_gains[mode] = 1;
790 	ath5k_eeprom_free_pcal_info(ah, mode);
796 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
805 	switch (mode) {
830 		ee->ee_n_piers[mode] = 3;
843 		ee->ee_n_piers[mode] = 3;
849 	for (i = 0; i < ee->ee_n_piers[mode]; i++) {
883 	return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
905 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
910 	u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
914 	for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
928 		for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1013 	ath5k_eeprom_free_pcal_info(ah, mode);
1019 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
1024 	u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1036 		/* ee_x_gain[mode] is x gain mask */
1037 		if ((ee->ee_x_gain[mode] >> i) & 0x1)
1040 	ee->ee_pd_gains[mode] = pd_gains;
1045 	switch (mode) {
1061 		/* NB: frequency piers parsed during mode init */
1071 		/* NB: frequency piers parsed during mode init */
1078 	for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1127 	return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1147  * if a mode is not supported, its section is missing -not zeroed-.
1151 /* Return the size of each section based on the mode and the number of pd
1154 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1159 	sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1160 	sz *= ee->ee_n_piers[mode];
1168 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1172 	switch (mode) {
1197 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1202 	u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1206 	for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1220 		for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1228 			if (pdg == ee->ee_pd_gains[mode] - 1)
1267 			if (pdg == ee->ee_pd_gains[mode] - 1)
1276 	ath5k_eeprom_free_pcal_info(ah, mode);
1282 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1287 	u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1299 		/* ee_x_gain[mode] is x gain mask */
1300 		if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1304 	ee->ee_pd_gains[mode] = pd_gains;
1309 	offset = ath5k_cal_data_offset_2413(ee, mode);
1310 	switch (mode) {
1323 		ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1331 		ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1339 	for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1461 	return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1473 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1483 	rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1484 	switch (mode) {
1488 		ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN;
1493 		ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1498 		ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1509 			    ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1530 			    ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1571 	int (*read_pcal)(struct ath5k_hw *hw, int mode);
1572 	int mode;
1585 	for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1586 	mode++) {
1587 		err = read_pcal(ah, mode);
1591 		err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1778 	u8 mode;
1780 	for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1781 		ath5k_eeprom_free_pcal_info(ah, mode);