Lines Matching defs:ah
45 * @ah: The &struct ath5k_hw
48 ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
50 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
51 ath5k_hw_reg_read(ah, AR5K_CR);
56 * @ah: The &struct ath5k_hw
59 ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
63 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
69 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
74 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
82 * @ah: The &struct ath5k_hw
85 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
87 return ath5k_hw_reg_read(ah, AR5K_RXDP);
92 * @ah: The &struct ath5k_hw
98 ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
100 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
101 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
106 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
117 * @ah: The &struct ath5k_hw
130 ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
134 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
137 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
140 if (ah->ah_version == AR5K_AR5210) {
141 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
146 switch (ah->ah_txq[queue].tqi_type) {
152 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
157 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
164 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
165 ath5k_hw_reg_read(ah, AR5K_CR);
168 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
172 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
180 * @ah: The &struct ath5k_hw
188 ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
193 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
196 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
199 if (ah->ah_version == AR5K_AR5210) {
200 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
205 switch (ah->ah_txq[queue].tqi_type) {
213 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
220 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
221 ath5k_hw_reg_read(ah, AR5K_CR);
228 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
234 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
238 (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);
242 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
243 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
249 pending = ath5k_hw_reg_read(ah,
257 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
260 ath5k_hw_reg_write(ah,
266 ath5k_hw_reg_write(ah,
268 AR5K_REG_SM(ath5k_hw_reg_read(ah,
274 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
279 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
285 pending = ath5k_hw_reg_read(ah,
291 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
295 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
303 AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
307 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
309 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
322 * @ah: The &struct ath5k_hw
328 ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
331 ret = ath5k_hw_stop_tx_dma(ah, queue);
333 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
342 * @ah: The &struct ath5k_hw
353 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
357 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
363 if (ah->ah_version == AR5K_AR5210) {
364 switch (ah->ah_txq[queue].tqi_type) {
379 return ath5k_hw_reg_read(ah, tx_reg);
384 * @ah: The &struct ath5k_hw
396 ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
400 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
406 if (ah->ah_version == AR5K_AR5210) {
407 switch (ah->ah_txq[queue].tqi_type) {
424 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
431 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
438 * @ah: The &struct ath5k_hw
453 ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
461 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
463 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
476 if (ah->ah_version == AR5K_AR5210)
477 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
479 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
488 ath5k_hw_set_imr(ah, imr);
500 * @ah: The &struct ath5k_hw
506 ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
508 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
513 * @ah: The @struct ath5k_hw
527 ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
537 if (ah->ah_version == AR5K_AR5210) {
539 isr = ath5k_hw_reg_read(ah, AR5K_ISR);
549 *interrupt_mask = (isr & AR5K_INT_COMMON) & ah->ah_imr;
575 pisr = ath5k_hw_reg_read(ah, AR5K_PISR);
581 sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0);
582 sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1);
583 sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2);
584 sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3);
585 sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4);
638 ath5k_hw_reg_write(ah, sisr0, AR5K_SISR0);
639 ath5k_hw_reg_write(ah, sisr1, AR5K_SISR1);
640 ath5k_hw_reg_write(ah, sisr2, AR5K_SISR2);
641 ath5k_hw_reg_write(ah, sisr3, AR5K_SISR3);
642 ath5k_hw_reg_write(ah, sisr4, AR5K_SISR4);
643 ath5k_hw_reg_write(ah, pisr_clear, AR5K_PISR);
645 ath5k_hw_reg_read(ah, AR5K_PISR);
651 *interrupt_mask = (pisr & AR5K_INT_COMMON) & ah->ah_imr;
653 ah->ah_txq_isr_txok_all = 0;
659 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
663 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
667 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
671 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
725 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
732 * @ah: The &struct ath5k_hw
740 ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
744 old_mask = ah->ah_imr;
752 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
753 ath5k_hw_reg_read(ah, AR5K_IER);
762 if (ah->ah_version != AR5K_AR5210) {
764 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
795 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
796 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
805 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
811 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);
814 ah->ah_imr = new_mask;
818 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
819 ath5k_hw_reg_read(ah, AR5K_IER);
832 * @ah: The &struct ath5k_hw
841 ath5k_hw_dma_init(struct ath5k_hw *ah)
856 if (ah->ah_version != AR5K_AR5210) {
857 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
859 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
864 if (ah->ah_version != AR5K_AR5210)
865 ath5k_hw_set_imr(ah, ah->ah_imr);
871 * @ah: The &struct ath5k_hw
881 ath5k_hw_dma_stop(struct ath5k_hw *ah)
887 ath5k_hw_set_imr(ah, 0);
890 err = ath5k_hw_stop_rx_dma(ah);
896 if (ah->ah_version != AR5K_AR5210) {
897 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
901 ath5k_hw_reg_read(ah, AR5K_ISR);
906 err = ath5k_hw_stop_tx_dma(ah, i);