Lines Matching defs:ah
62 * @ah: The &struct ath5k_hw
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
86 ATH5K_ERR(ah, "noise immunity level %d out of range",
91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE,
95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE,
97 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
100 ah->ani_state.noise_imm_level = level;
101 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
106 * @ah: The &struct ath5k_hw
111 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
116 level > ah->ani_state.max_spur_level) {
117 ATH5K_ERR(ah, "spur immunity level %d out of range",
122 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
125 ah->ani_state.spur_level = level;
126 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
131 * @ah: The &struct ath5k_hw
135 ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
140 ATH5K_ERR(ah, "firstep level %d out of range", level);
144 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
147 ah->ani_state.firstep_level = level;
148 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
153 * @ah: The &struct ath5k_hw
157 ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
166 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
168 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
170 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
172 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
174 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
176 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
180 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
183 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
186 ah->ani_state.ofdm_weak_sig = on;
187 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
193 * @ah: The &struct ath5k_hw
197 ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
200 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
202 ah->ani_state.cck_weak_sig = on;
203 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
214 * @ah: The &struct ath5k_hw
223 ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
226 int rssi = ewma_beacon_rssi_read(&ah->ah_beacon_rssi_avg);
228 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "raise immunity (%s)",
233 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level + 1);
239 as->spur_level < ah->ani_state.max_spur_level) {
240 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1);
245 if (ah->opmode == NL80211_IFTYPE_AP) {
247 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
258 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
263 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
264 ath5k_ani_set_spur_immunity_level(ah, 0);
269 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
275 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
278 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
280 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
282 } else if (ah->ah_current_channel->band == NL80211_BAND_2GHZ) {
285 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
288 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
290 ath5k_ani_set_firstep_level(ah, 0);
296 ath5k_ani_set_cck_weak_signal_detection(ah, false);
303 * @ah: The &struct ath5k_hw
310 ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
312 int rssi = ewma_beacon_rssi_read(&ah->ah_beacon_rssi_avg);
314 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "lower immunity");
316 if (ah->opmode == NL80211_IFTYPE_AP) {
319 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1);
332 ath5k_ani_set_ofdm_weak_signal_detection(ah,
337 ath5k_ani_set_firstep_level(ah,
344 ath5k_ani_set_firstep_level(ah,
353 ath5k_ani_set_spur_immunity_level(ah, as->spur_level - 1);
359 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1);
366 * @ah: The &struct ath5k_hw
374 ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
376 struct ath_common *common = ath5k_hw_common(ah);
394 * @ah: The &struct ath5k_hw
406 ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah,
411 if (!ah->ah_capabilities.cap_has_phyerr_counters)
414 ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1);
415 cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2);
418 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
420 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
464 * @ah: The &struct ath5k_hw
475 ath5k_ani_calibration(struct ath5k_hw *ah)
477 struct ath5k_ani_state *as = &ah->ani_state;
483 listen = ath5k_hw_ani_get_listen_time(ah, as);
489 ath5k_ani_save_and_clear_phy_errors(ah, as);
496 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
498 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
505 ath5k_ani_raise_immunity(ah, as, ofdm_flag);
511 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
516 ath5k_ani_lower_immunity(ah, as);
529 * @ah: The &struct ath5k_hw
539 ath5k_ani_mib_intr(struct ath5k_hw *ah)
541 struct ath5k_ani_state *as = &ah->ani_state;
545 if (!ah->ah_capabilities.cap_has_phyerr_counters)
549 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
550 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
552 if (ah->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
558 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0)
563 tasklet_schedule(&ah->ani_tasklet);
569 * @ah: The &struct ath5k_hw
576 ath5k_ani_phy_error_report(struct ath5k_hw *ah,
579 struct ath5k_ani_state *as = &ah->ani_state;
584 tasklet_schedule(&ah->ani_tasklet);
588 tasklet_schedule(&ah->ani_tasklet);
599 * @ah: The &struct ath5k_hw
604 ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
606 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
608 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
610 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK);
611 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK);
614 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
615 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
620 * @ah: The &struct ath5k_hw
625 ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
627 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1);
628 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2);
629 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK);
630 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK);
633 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
634 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
639 * @ah: The &struct ath5k_hw
645 ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
648 if (ah->ah_version < AR5K_AR5212)
652 ATH5K_ERR(ah, "ANI mode %d out of range", mode);
657 memset(&ah->ani_state, 0, sizeof(ah->ani_state));
660 if (ah->ah_mac_srev < AR5K_SREV_AR2414)
661 ah->ani_state.max_spur_level = 7;
663 ah->ani_state.max_spur_level = 2;
667 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI off\n");
669 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
671 ath5k_ani_set_noise_immunity_level(ah, 0);
672 ath5k_ani_set_spur_immunity_level(ah, 0);
673 ath5k_ani_set_firstep_level(ah, 0);
674 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
675 ath5k_ani_set_cck_weak_signal_detection(ah, true);
677 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
679 ath5k_ani_set_noise_immunity_level(ah,
681 ath5k_ani_set_spur_immunity_level(ah,
682 ah->ani_state.max_spur_level);
683 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
684 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
685 ath5k_ani_set_cck_weak_signal_detection(ah, false);
687 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI auto\n");
688 ath5k_ani_set_noise_immunity_level(ah, 0);
689 ath5k_ani_set_spur_immunity_level(ah, 0);
690 ath5k_ani_set_firstep_level(ah, 0);
691 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
692 ath5k_ani_set_cck_weak_signal_detection(ah, false);
700 if (ah->ah_capabilities.cap_has_phyerr_counters)
701 ath5k_enable_phy_err_counters(ah);
703 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) |
706 if (ah->ah_capabilities.cap_has_phyerr_counters)
707 ath5k_disable_phy_err_counters(ah);
709 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) &
713 ah->ani_state.ani_mode = mode;
725 * @ah: The &struct ath5k_hw
730 ath5k_ani_print_counters(struct ath5k_hw *ah)
733 pr_notice("ACK fail\t%d\n", ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
734 pr_notice("RTS fail\t%d\n", ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));
735 pr_notice("RTS success\t%d\n", ath5k_hw_reg_read(ah, AR5K_RTS_OK));
736 pr_notice("FCS error\t%d\n", ath5k_hw_reg_read(ah, AR5K_FCS_FAIL));
739 pr_notice("tx\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX));
740 pr_notice("rx\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX));
741 pr_notice("busy\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR));
742 pr_notice("cycles\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE));
745 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1));
747 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2));
749 ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT));
751 ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT));