Lines Matching refs:info0
17 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) |
21 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic);
35 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
37 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI,
43 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS;
45 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
67 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
69 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
72 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI,
76 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS;
79 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE;
80 desc->info0 |=
86 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE;
89 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL;
91 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
105 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
107 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
110 desc->info0 =
216 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
274 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo);
287 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0);
310 msdu->buf_addr_info.info0)) {
328 desc->info0);
330 desc->info0);
340 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) !=
360 wbm_desc->info0);
368 wbm_desc->info0);
387 wbm_desc->info0);
390 wbm_desc->info0);
394 wbm_desc->info0);
397 wbm_desc->info0);
413 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0);
426 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
442 desc->hdr.info0);
445 desc->hdr.info0);
453 desc->info0),
455 desc->info0));
505 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0);
507 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0);
519 desc->hdr.info0);
522 desc->hdr.info0);
525 desc->info0);
538 desc->hdr.info0);
541 desc->hdr.info0);
545 desc->info0);
548 desc->info0);
554 desc->info0);
558 desc->info0);
561 desc->info0);
564 desc->info0);
567 desc->info0);
580 desc->hdr.info0);
583 desc->hdr.info0);
587 desc->info0);
590 desc->info0);
608 desc->hdr.info0);
611 desc->hdr.info0);
615 desc->info0);
618 desc->info0);
638 desc->hdr.info0);
641 desc->hdr.info0);
645 desc->info0);
674 desc->info0);
677 desc->info0);
715 qdesc->info0 =
727 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1);
729 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE,
737 qdesc->info0 |=
747 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1);
803 desc->cmd.info0 =
879 u32 info0, info1, value;
890 __le32_to_cpu(ppdu_start->info0));
899 info0 = __le32_to_cpu(eu_stats->info0);
927 info0);
972 info0 = __le32_to_cpu(ht_sig->info0);
975 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0);
976 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0);
1008 __le32_to_cpu(lsigb->info0));
1017 __le32_to_cpu(lsiga->info0));
1028 info0 = __le32_to_cpu(vht_sig->info0);
1047 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;
1048 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);
1054 info0);
1058 info0);
1077 info0 = __le32_to_cpu(he_sig_a->info0);
1080 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0);
1108 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0);
1111 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0);
1114 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0);
1117 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0);
1122 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0);
1139 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0);
1144 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0);
1148 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0);
1180 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1197 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1216 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
1239 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0);
1243 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0);
1257 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0);
1262 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1267 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0);
1310 info0);
1327 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0);
1331 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0);
1340 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1344 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0);
1347 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0);
1363 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
1366 info0);
1377 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
1383 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0);
1387 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0);
1392 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0);
1397 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1;
1404 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
1416 info0);
1420 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0);
1425 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0);
1431 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0);
1437 info0) + 1;
1439 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF;
1456 __le32_to_cpu(rssi->info0));
1482 __le32_to_cpu(ppdu_rx_duration->info0));
1551 rx_mpdu_desc_info_details->info0);
1558 buf_addr_info->info0);
1580 rx_mpdu_desc_info_details->info0);
1588 buf_addr_info->info0);
1594 status_buf_addr_info->info0);
1603 sw_mon_ring->info0);