ath/ath10k/hw.c

1 // SPDX-License-Identifier: ISC
3  * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
11 #include "hw.h"
13 #include "wmi-ops.h"
557 	survey->filled |= SURVEY_INFO_TIME |
560 	wraparound_type = ar->hw_params.cc_wraparound_type;
567 				survey->filled &= ~SURVEY_INFO_TIME_BUSY;
582 	cc -= cc_prev - cc_fix;
583 	rcc -= rcc_prev - rcc_fix;
585 	survey->time = CCNT_TO_MSEC(ar, cc);
586 	survey->time_busy = CCNT_TO_MSEC(ar, rcc);
606 	mutex_lock(&ar->conf_mutex);
609 	if ((ar->state != ATH10K_STATE_ON) &&
610 	    (ar->state != ATH10K_STATE_RESTARTED)) {
611 		spin_lock_bh(&ar->data_lock);
613 		ar->fw_coverage.coverage_class = value;
614 		spin_unlock_bh(&ar->data_lock);
630 		value = ar->fw_coverage.coverage_class;
635 	if (value == ar->fw_coverage.coverage_class &&
636 	    slottime_reg == ar->fw_coverage.reg_slottime_conf &&
637 	    timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
638 	    phyclk_reg == ar->fw_coverage.reg_phyclk)
642 	if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
643 		ar->fw_coverage.reg_slottime_orig = slottime_reg;
644 	if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
645 		ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
646 	ar->fw_coverage.reg_phyclk = phyclk_reg;
649 	slottime_reg = ar->fw_coverage.reg_slottime_orig;
650 	timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
664 			    "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
671 	 * delay (3us per coverage class).
719 	spin_lock_bh(&ar->data_lock);
720 	ar->fw_coverage.coverage_class = value;
721 	spin_unlock_bh(&ar->data_lock);
723 	ar->fw_coverage.reg_slottime_conf = slottime_reg;
724 	ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
727 	mutex_unlock(&ar->conf_mutex);
731  * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
747 	struct ath10k_hw_params *hw;
750 	hw = &ar->hw_params;
752 	if (ar->regs->core_clk_div_address == 0 ||
753 	    ar->regs->cpu_pll_init_address == 0 ||
754 	    ar->regs->cpu_speed_address == 0)
755 		return -EINVAL;
757 	clk_div_addr = ar->regs->core_clk_div_address;
758 	pll_init_addr = ar->regs->cpu_pll_init_address;
759 	speed_addr = ar->regs->cpu_speed_address;
761 	/* Read efuse register to find out the right hw clock configuration */
765 		return -EINVAL;
767 	/* sanitize if the hw refclk index is out of the boundary */
769 		return -EINVAL;
771 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];
777 		return -EINVAL;
780 	reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |
781 		    SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));
784 		return -EINVAL;
786 	/* Set the correct settle time value to pll_settle register */
790 		return -EINVAL;
793 	reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);
796 		return -EINVAL;
802 		return -EINVAL;
808 		return -EINVAL;
815 		return -EINVAL;
821 		return -EINVAL;
823 	reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |
824 		    SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |
828 		return -EINVAL;
836 			return -EINVAL;
841 		wait_limit--;
847 		return -EINVAL;
853 		return -EINVAL;
859 		return -EINVAL;
867 			return -EINVAL;
872 		wait_limit--;
878 		return -EINVAL;
884 		return -EINVAL;
890 		return -EINVAL;
896 		return -EINVAL;
901 		return -EINVAL;
908 		return -EINVAL;
911 	ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,
912 				      sizeof(hw->target_cpu_freq));
914 		return -EINVAL;
949 		size = REGION_ACCESS_SIZE_LIMIT - addr;
950 		remain_size = length - size;
1020 		return -EINVAL;
1026 	if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) {
1029 			   hdr->magic_num);
1030 		return -EINVAL;
1033 	if (hdr->file_flags != 0) {
1036 			   hdr->file_flags);
1037 		return -EINVAL;
1040 	metadata = (struct bmi_segmented_metadata *)hdr->data;
1041 	left = length - sizeof(*hdr);
1047 			ret = -EINVAL;
1050 		base_addr = __le32_to_cpu(metadata->addr);
1051 		base_len = __le32_to_cpu(metadata->length);
1052 		buf = metadata->data;
1053 		left -= sizeof(*metadata);
1072 			ret = -EINVAL;
1080 				ret = -EINVAL;
1100 		left -= base_len;
1111 	return (resp->data_tx_completion.flags2 & HTT_TX_CMPL_FLAG_DATA_RSSI);
1116 	return (resp->data_tx_completion.flags2 &
1125 	if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_RETRIES)
1129 	if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_TIMESTAMP)