net/wan/wanxl.c

72 	u8 __iomem *plx;	/* PLX PCI9060 virtual base address */
264 	while ((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
266 		writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
310 	       port->card->plx + PLX_DOORBELL_TO_CARD);
396 	u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
438 	       port->card->plx + PLX_DOORBELL_TO_CARD);
480 	writel(cmd, card->plx + PLX_MAILBOX_1);
482 		if (readl(card->plx + PLX_MAILBOX_1) == 0)
493 	u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
495 	writel(0x80, card->plx + PLX_MAILBOX_0);
496 	writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
497 	readl(card->plx + PLX_CONTROL); /* wait for posted write */
499 	writel(old_value, card->plx + PLX_CONTROL);
500 	readl(card->plx + PLX_CONTROL); /* wait for posted write */
527 	if (card->plx)
528 		iounmap(card->plx);
639 	card->plx = ioremap(plx_phy, 0x70);
640 	if (!card->plx) {
651 	while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
675 	ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
725 	writel(0, card->plx + PLX_MAILBOX_5);
735 		stat = readl(card->plx + PLX_MAILBOX_5);