Lines Matching +full:pse +full:- +full:pis
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pse-pd/pse.h>
27 * struct pse_control - a PSE control
28 * @pcdev: a pointer to the PSE controller device
29 * this PSE control belongs to
30 * @ps: PSE PI supply of the PSE control
31 * @list: list entry for the pcdev's PSE controller list
32 * @id: ID of the PSE line in the PSE controller device
34 * @attached_phydev: PHY device pointer attached by the PSE control
46 * struct pse_power_domain - a PSE power domain
68 ret = of_property_read_string_index(node, "pairset-names",
73 if (!strcmp(name, "alternative-a")) {
74 pi->pairset[pairset_num].pinout = ALTERNATIVE_A;
75 } else if (!strcmp(name, "alternative-b")) {
76 pi->pairset[pairset_num].pinout = ALTERNATIVE_B;
78 pr_err("pse: wrong pairset-names value %s (%pOF)\n",
80 return -EINVAL;
85 return -ENODEV;
87 pi->pairset[pairset_num].np = pairset_np;
93 * of_load_pse_pi_pairsets - load PSE PI pairsets pinout and polarity
95 * @pi: a pointer of the PSE PI to fill
106 ret = of_property_count_strings(node, "pairset-names");
108 pr_err("pse: amount of pairsets and pairset-names is not equal %d != %d (%pOF)\n",
110 return -EINVAL;
120 pi->pairset[0].pinout == pi->pairset[1].pinout) {
121 pr_err("pse: two PI pairsets can not have identical pinout (%pOF)",
123 ret = -EINVAL;
129 of_node_put(pi->pairset[0].np);
130 pi->pairset[0].np = NULL;
131 of_node_put(pi->pairset[1].np);
132 pi->pairset[1].np = NULL;
142 for (i = 0; i < pcdev->nr_lines; i++) {
143 of_node_put(pcdev->pi[i].pairset[0].np);
144 of_node_put(pcdev->pi[i].pairset[1].np);
145 of_node_put(pcdev->pi[i].np);
147 kfree(pcdev->pi);
151 * of_load_pse_pis - load all the PSE PIs
152 * @pcdev: a pointer to the PSE controller device
158 struct device_node *np = pcdev->dev->of_node;
159 struct device_node *node, *pis;
163 return -ENODEV;
165 pcdev->pi = kcalloc(pcdev->nr_lines, sizeof(*pcdev->pi), GFP_KERNEL);
166 if (!pcdev->pi)
167 return -ENOMEM;
169 pis = of_get_child_by_name(np, "pse-pis");
170 if (!pis) {
171 /* no description of PSE PIs */
172 pcdev->no_of_pse_pi = true;
176 for_each_child_of_node(pis, node) {
180 if (!of_node_name_eq(node, "pse-pi"))
185 dev_err(pcdev->dev,
191 if (id >= pcdev->nr_lines) {
192 dev_err(pcdev->dev,
194 id, pcdev->nr_lines, node);
195 ret = -EINVAL;
199 if (pcdev->pi[id].np) {
200 dev_err(pcdev->dev,
202 pcdev->pi[id].np, node);
203 ret = -EINVAL;
214 dev_err(pcdev->dev,
217 ret = -EINVAL;
223 memcpy(&pcdev->pi[id], &pi, sizeof(pi));
226 of_node_put(pis);
232 of_node_put(pis);
237 * pse_control_find_net_by_id - Find net attached to the pse control id
238 * @pcdev: a pointer to the PSE
239 * @id: index of the PSE control
251 list_for_each_entry(psec, &pcdev->pse_control_head, list) {
252 if (psec->id == id) {
253 kref_get(&psec->refcnt);
263 * pse_control_get_netdev - Return netdev associated to a PSE control
264 * @psec: PSE control pointer
272 if (!psec || !psec->attached_phydev)
275 return psec->attached_phydev->attached_dev;
279 * pse_pi_is_hw_enabled - Is PI enabled at the hardware level
280 * @pcdev: a pointer to the PSE controller device
291 ret = pcdev->ops->pi_get_admin_state(pcdev, id, &admin_state);
304 * pse_pi_is_admin_enable_pending - Check if PI is in admin enable pending state
307 * @pcdev: a pointer to the PSE controller device
314 * which PIs need to have power delivery attempted again.
325 if (!pcdev->pi[id].admin_state_enabled ||
326 !pcdev->pi[id].isr_pd_detected)
330 /* PSE PI is already enabled at hardware level */
342 * pse_pw_d_retry_power_delivery - Retry power delivery for pending ports in a
343 * PSE power domain
344 * @pcdev: a pointer to the PSE controller device
345 * @pw_d: a pointer to the PSE power domain
351 * receive power, especially in over-budget conditions.
358 for (i = 0; i < pcdev->nr_lines; i++) {
359 int prio_max = pcdev->nr_lines;
362 if (pcdev->pi[i].pw_d != pw_d)
371 if (pcdev->pi[i].prio > prio_max)
375 if (ret == -ERANGE)
376 prio_max = pcdev->pi[i].prio;
381 * pse_pw_d_is_sw_pw_control - Determine if power control is software managed
382 * @pcdev: a pointer to the PSE controller device
383 * @pw_d: a pointer to the PSE power domain
390 * - When the budget evaluation strategy is set to static
391 * - When the budget evaluation strategy is disabled but the PSE controller
403 if (pw_d->budget_eval_strategy == PSE_BUDGET_EVAL_STRAT_STATIC)
405 if (pw_d->budget_eval_strategy == PSE_BUDGET_EVAL_STRAT_DISABLED &&
406 pcdev->ops->pi_enable && pcdev->irq)
418 ops = pcdev->ops;
419 if (!ops->pi_get_admin_state)
420 return -EOPNOTSUPP;
423 mutex_lock(&pcdev->lock);
424 if (pse_pw_d_is_sw_pw_control(pcdev, pcdev->pi[id].pw_d)) {
425 ret = pcdev->pi[id].admin_state_enabled;
432 mutex_unlock(&pcdev->lock);
438 * pse_pi_deallocate_pw_budget - Deallocate power budget of the PI
439 * @pi: a pointer to the PSE PI
443 if (!pi->pw_d || !pi->pw_allocated_mW)
446 regulator_free_power_budget(pi->pw_d->supply, pi->pw_allocated_mW);
447 pi->pw_allocated_mW = 0;
451 * _pse_pi_disable - Call disable operation. Assumes the PSE lock has been
453 * @pcdev: a pointer to the PSE
454 * @id: index of the PSE control
460 const struct pse_controller_ops *ops = pcdev->ops;
463 if (!ops->pi_disable)
464 return -EOPNOTSUPP;
466 ret = ops->pi_disable(pcdev, id);
470 pse_pi_deallocate_pw_budget(&pcdev->pi[id]);
472 if (pse_pw_d_is_sw_pw_control(pcdev, pcdev->pi[id].pw_d))
473 pse_pw_d_retry_power_delivery(pcdev, pcdev->pi[id].pw_d);
479 * pse_disable_pi_pol - Disable a PI on a power budget policy
480 * @pcdev: a pointer to the PSE
481 * @id: index of the PSE PI
491 dev_dbg(pcdev->dev, "Disabling PI %d to free power budget\n", id);
499 kfifo_in_spinlocked(&pcdev->ntf_fifo, &ntf, 1, &pcdev->ntf_fifo_lock);
500 schedule_work(&pcdev->ntf_work);
506 * pse_disable_pi_prio - Disable all PIs of a given priority inside a PSE
508 * @pcdev: a pointer to the PSE
509 * @pw_d: a pointer to the PSE power domain
520 for (i = 0; i < pcdev->nr_lines; i++) {
523 if (pcdev->pi[i].prio != prio ||
524 pcdev->pi[i].pw_d != pw_d ||
537 * pse_pi_allocate_pw_budget_static_prio - Allocate power budget for the PI
540 * @pcdev: a pointer to the PSE
541 * @id: index of the PSE control
547 * lower-priority ports (higher priority numbers) are turned off first.
555 struct pse_pi *pi = &pcdev->pi[id];
558 _prio = pcdev->nr_lines;
559 while (regulator_request_power_budget(pi->pw_d->supply, pw_req) == -ERANGE) {
560 if (_prio <= pi->prio) {
564 return -ERANGE;
567 ret = pse_disable_pi_prio(pcdev, pi->pw_d, _prio);
571 _prio--;
574 pi->pw_allocated_mW = pw_req;
579 * pse_pi_allocate_pw_budget - Allocate power budget for the PI
580 * @pcdev: a pointer to the PSE
581 * @id: index of the PSE control
590 struct pse_pi *pi = &pcdev->pi[id];
592 if (!pi->pw_d)
596 if (pi->pw_d->budget_eval_strategy == PSE_BUDGET_EVAL_STRAT_STATIC)
604 * _pse_pi_delivery_power_sw_pw_ctrl - Enable PSE PI in case of software power
605 * control. Assumes the PSE lock has been
607 * @pcdev: a pointer to the PSE
608 * @id: index of the PSE control
617 const struct pse_controller_ops *ops = pcdev->ops;
618 struct pse_pi *pi = &pcdev->pi[id];
621 if (!ops->pi_get_pw_req) {
623 ret = ops->pi_enable(pcdev, id);
631 ret = ops->pi_get_pw_req(pcdev, id);
640 if (ops->pi_get_pw_limit) {
641 ret = ops->pi_get_pw_limit(pcdev, id);
653 ret = ops->pi_enable(pcdev, id);
671 ops = pcdev->ops;
672 if (!ops->pi_enable)
673 return -EOPNOTSUPP;
676 mutex_lock(&pcdev->lock);
677 if (pse_pw_d_is_sw_pw_control(pcdev, pcdev->pi[id].pw_d)) {
681 if (pcdev->pi[id].isr_pd_detected) {
686 if (!ret || ret == -ERANGE) {
687 pcdev->pi[id].admin_state_enabled = 1;
690 mutex_unlock(&pcdev->lock);
694 ret = ops->pi_enable(pcdev, id);
696 pcdev->pi[id].admin_state_enabled = 1;
697 mutex_unlock(&pcdev->lock);
709 pi = &pcdev->pi[id];
710 mutex_lock(&pcdev->lock);
713 pi->admin_state_enabled = 0;
715 mutex_unlock(&pcdev->lock);
725 ops = pcdev->ops;
726 if (!ops->pi_get_voltage)
727 return -EOPNOTSUPP;
730 return ops->pi_get_voltage(pcdev, id);
738 mutex_lock(&pcdev->lock);
740 mutex_unlock(&pcdev->lock);
752 ops = pcdev->ops;
754 if (!ops->pi_get_pw_limit || !ops->pi_get_voltage)
755 return -EOPNOTSUPP;
757 mutex_lock(&pcdev->lock);
758 ret = ops->pi_get_pw_limit(pcdev, id);
765 dev_err(pcdev->dev, "Voltage null\n");
766 ret = -ERANGE;
779 mutex_unlock(&pcdev->lock);
791 ops = pcdev->ops;
792 if (!ops->pi_set_pw_limit || !ops->pi_get_voltage)
793 return -EOPNOTSUPP;
796 return -ERANGE;
799 mutex_lock(&pcdev->lock);
802 dev_err(pcdev->dev, "Voltage null\n");
803 ret = -ERANGE;
813 ret = ops->pi_set_pw_limit(pcdev, id, mW);
815 mutex_unlock(&pcdev->lock);
838 rinit_data = devm_kzalloc(pcdev->dev, sizeof(*rinit_data),
841 return -ENOMEM;
843 rdesc = devm_kzalloc(pcdev->dev, sizeof(*rdesc), GFP_KERNEL);
845 return -ENOMEM;
848 * PSE PI id for the well functioning of the PSE controls.
850 rdesc->id = id;
851 rdesc->name = name;
852 rdesc->type = REGULATOR_VOLTAGE;
853 rdesc->ops = &pse_pi_ops;
854 rdesc->owner = pcdev->owner;
856 rinit_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
858 if (pcdev->ops->pi_set_pw_limit)
859 rinit_data->constraints.valid_ops_mask |=
862 rinit_data->supply_regulator = "vpwr";
864 rconfig.dev = pcdev->dev;
867 rconfig.of_node = pcdev->pi[id].np;
869 rdev = devm_regulator_register(pcdev->dev, rdesc, &rconfig);
871 dev_err_probe(pcdev->dev, PTR_ERR(rdev),
876 pcdev->pi[id].rdev = rdev;
887 regulator_put(pw_d->supply);
888 xa_erase(&pse_pw_d_map, pw_d->id);
893 * pse_flush_pw_ds - flush all PSE power domains of a PSE
894 * @pcdev: a pointer to the initialized PSE controller device
901 for (i = 0; i < pcdev->nr_lines; i++) {
902 if (!pcdev->pi[i].pw_d)
905 pw_d = xa_load(&pse_pw_d_map, pcdev->pi[i].pw_d->id);
909 kref_put_mutex(&pw_d->refcnt, __pse_pw_d_release,
915 * devm_pse_alloc_pw_d - allocate a new PSE power domain for a device
916 * @dev: device that is registering this PSE power domain
918 * Return: Pointer to the newly allocated PSE power domain or error pointers
927 return ERR_PTR(-ENOMEM);
934 kref_init(&pw_d->refcnt);
935 pw_d->id = index;
940 * pse_register_pw_ds - register the PSE power domains for a PSE
941 * @pcdev: a pointer to the PSE controller device
950 for (i = 0; i < pcdev->nr_lines; i++) {
951 struct regulator_dev *rdev = pcdev->pi[i].rdev;
958 * We need a regulator parent to register a PSE power domain
960 if (!rdev || !rdev->supply)
964 /* Power supply already registered as a PSE power
967 if (regulator_is_equal(pw_d->supply, rdev->supply)) {
969 pcdev->pi[i].pw_d = pw_d;
974 kref_get(&pw_d->refcnt);
978 pw_d = devm_pse_alloc_pw_d(pcdev->dev);
984 supply = regulator_get(&rdev->dev, rdev->supply_name);
986 xa_erase(&pse_pw_d_map, pw_d->id);
991 pw_d->supply = supply;
992 if (pcdev->supp_budget_eval_strategies)
993 pw_d->budget_eval_strategy = pcdev->supp_budget_eval_strategies;
995 pw_d->budget_eval_strategy = PSE_BUDGET_EVAL_STRAT_DISABLED;
996 kref_init(&pw_d->refcnt);
997 pcdev->pi[i].pw_d = pw_d;
1006 * pse_send_ntf_worker - Worker to send PSE notifications
1009 * Manage and send PSE netlink notifications using a workqueue to avoid
1019 while (kfifo_out(&pcdev->ntf_fifo, &ntf, 1)) {
1034 * pse_controller_register - register a PSE controller device
1035 * @pcdev: a pointer to the initialized PSE controller device
1044 mutex_init(&pcdev->lock);
1045 INIT_LIST_HEAD(&pcdev->pse_control_head);
1046 spin_lock_init(&pcdev->ntf_fifo_lock);
1047 ret = kfifo_alloc(&pcdev->ntf_fifo, pcdev->nr_lines, GFP_KERNEL);
1049 dev_err(pcdev->dev, "failed to allocate kfifo notifications\n");
1052 INIT_WORK(&pcdev->ntf_work, pse_send_ntf_worker);
1054 if (!pcdev->nr_lines)
1055 pcdev->nr_lines = 1;
1057 if (!pcdev->ops->pi_get_admin_state ||
1058 !pcdev->ops->pi_get_pw_status) {
1059 dev_err(pcdev->dev,
1061 return -EINVAL;
1068 if (pcdev->ops->setup_pi_matrix) {
1069 ret = pcdev->ops->setup_pi_matrix(pcdev);
1077 reg_name_len = strlen(dev_name(pcdev->dev)) + 18;
1080 for (i = 0; i < pcdev->nr_lines; i++) {
1083 /* Do not register regulator for PIs not described */
1084 if (!pcdev->no_of_pse_pi && !pcdev->pi[i].np)
1087 reg_name = devm_kzalloc(pcdev->dev, reg_name_len, GFP_KERNEL);
1089 return -ENOMEM;
1091 snprintf(reg_name, reg_name_len, "pse-%s_pi%d",
1092 dev_name(pcdev->dev), i);
1104 list_add(&pcdev->list, &pse_controller_list);
1112 * pse_controller_unregister - unregister a PSE controller device
1113 * @pcdev: a pointer to the PSE controller device
1119 if (pcdev->irq)
1120 disable_irq(pcdev->irq);
1121 cancel_work_sync(&pcdev->ntf_work);
1122 kfifo_free(&pcdev->ntf_fifo);
1124 list_del(&pcdev->list);
1135 * devm_pse_controller_register - resource managed pse_controller_register()
1136 * @dev: device that is registering this PSE controller
1137 * @pcdev: a pointer to the initialized PSE controller device
1139 * Managed pse_controller_register(). For PSE controllers registered by
1154 return -ENOMEM;
1176 * pse_to_regulator_notifs - Convert PSE notifications to Regulator
1178 * @notifs: PSE notifications
1195 * pse_set_config_isr - Set PSE control config according to the PSE
1197 * @pcdev: a pointer to the PSE
1198 * @id: index of the PSE control
1199 * @notifs: PSE event notifications
1214 dev_dbg(pcdev->dev,
1217 return -EINVAL;
1223 pcdev->pi[id].isr_pd_detected = true;
1224 if (pcdev->pi[id].admin_state_enabled) {
1227 if (ret == -ERANGE)
1231 if (pcdev->pi[id].admin_state_enabled &&
1232 pcdev->pi[id].isr_pd_detected)
1234 pcdev->pi[id].isr_pd_detected = false;
1241 * pse_isr - IRQ handler for PSE
1245 * Return: irqreturn_t - status of IRQ
1255 desc = &h->desc;
1256 pcdev = h->pcdev;
1259 memset(h->notifs, 0, pcdev->nr_lines * sizeof(*h->notifs));
1260 mutex_lock(&pcdev->lock);
1261 ret = desc->map_event(irq, pcdev, h->notifs, ¬ifs_mask);
1263 mutex_unlock(&pcdev->lock);
1267 for_each_set_bit(i, ¬ifs_mask, pcdev->nr_lines) {
1272 if (!pcdev->pi[i].rdev)
1275 notifs = h->notifs[i];
1276 if (pse_pw_d_is_sw_pw_control(pcdev, pcdev->pi[i].pw_d)) {
1282 dev_dbg(h->pcdev->dev,
1283 "Sending PSE notification EVT 0x%lx\n", notifs);
1287 kfifo_in_spinlocked(&pcdev->ntf_fifo, &ntf, 1,
1288 &pcdev->ntf_fifo_lock);
1289 schedule_work(&pcdev->ntf_work);
1292 regulator_notifier_call_chain(pcdev->pi[i].rdev, rnotifs,
1296 mutex_unlock(&pcdev->lock);
1302 * devm_pse_irq_helper - Register IRQ based PSE event notifier
1303 * @pcdev: a pointer to the PSE
1306 * @d: PSE interrupt description
1313 struct device *dev = pcdev->dev;
1319 if (!d || !d->map_event || !d->name)
1320 return -EINVAL;
1324 return -ENOMEM;
1326 h->pcdev = pcdev;
1327 h->desc = *d;
1330 irq_name_len = strlen(dev_name(pcdev->dev)) + 5 + strlen(d->name) + 1;
1333 return -ENOMEM;
1335 snprintf(irq_name, irq_name_len, "pse-%s:%s", dev_name(pcdev->dev),
1336 d->name);
1338 h->notifs = devm_kcalloc(dev, pcdev->nr_lines,
1339 sizeof(*h->notifs), GFP_KERNEL);
1340 if (!h->notifs)
1341 return -ENOMEM;
1347 dev_err(pcdev->dev, "Failed to request IRQ %d\n", irq);
1349 pcdev->irq = irq;
1354 /* PSE control section */
1363 if (psec->pcdev->pi[psec->id].admin_state_enabled)
1364 regulator_disable(psec->ps);
1365 devm_regulator_put(psec->ps);
1367 module_put(psec->pcdev->owner);
1369 list_del(&psec->list);
1377 kref_put(&psec->refcnt, __pse_control_release);
1381 * pse_control_put - free the PSE control
1382 * @psec: PSE control pointer
1404 list_for_each_entry(psec, &pcdev->pse_control_head, list) {
1405 if (psec->id == index) {
1406 kref_get(&psec->refcnt);
1413 return ERR_PTR(-ENOMEM);
1415 if (!try_module_get(pcdev->owner)) {
1416 ret = -ENODEV;
1420 if (!pcdev->ops->pi_get_admin_state) {
1421 ret = -EOPNOTSUPP;
1433 pcdev->pi[index].admin_state_enabled = ret;
1434 psec->ps = devm_regulator_get_exclusive(pcdev->dev,
1435 rdev_get_name(pcdev->pi[index].rdev));
1436 if (IS_ERR(psec->ps)) {
1437 ret = PTR_ERR(psec->ps);
1441 psec->pcdev = pcdev;
1442 list_add(&psec->list, &pcdev->pse_control_head);
1443 psec->id = index;
1444 psec->attached_phydev = phydev;
1445 kref_init(&psec->refcnt);
1450 module_put(pcdev->owner);
1458 * of_pse_match_pi - Find the PSE PI id matching the device node phandle
1459 * @pcdev: a pointer to the PSE controller device
1462 * Return: id of the PSE PI, -EINVAL if not found
1469 for (i = 0; i < pcdev->nr_lines; i++) {
1470 if (pcdev->pi[i].np == np)
1474 return -EINVAL;
1478 * psec_id_xlate - translate pse_spec to the PSE line number according
1479 * to the number of pse-cells in case of no pse_pi node
1480 * @pcdev: a pointer to the PSE controller device
1481 * @pse_spec: PSE line specifier as found in the device tree
1483 * Return: 0 if #pse-cells = <0>. Return PSE line number otherwise.
1488 if (!pcdev->of_pse_n_cells)
1491 if (pcdev->of_pse_n_cells > 1 ||
1492 pse_spec->args[0] >= pcdev->nr_lines)
1493 return -EINVAL;
1495 return pse_spec->args[0];
1508 return ERR_PTR(-EINVAL);
1510 ret = of_parse_phandle_with_args(node, "pses", "#pse-cells", 0, &args);
1517 if (!r->no_of_pse_pi) {
1524 } else if (args.np == r->dev->of_node) {
1531 psec = ERR_PTR(-EPROBE_DEFER);
1535 if (WARN_ON(args.args_count != pcdev->of_pse_n_cells)) {
1536 psec = ERR_PTR(-EINVAL);
1540 if (pcdev->no_of_pse_pi) {
1560 * pse_get_sw_admin_state - Convert the software admin state to c33 or podl
1562 * @psec: PSE control pointer
1568 struct pse_pi *pi = &psec->pcdev->pi[psec->id];
1571 if (pi->admin_state_enabled)
1572 admin_state->podl_admin_state =
1575 admin_state->podl_admin_state =
1579 if (pi->admin_state_enabled)
1580 admin_state->c33_admin_state =
1583 admin_state->c33_admin_state =
1589 * pse_ethtool_get_status - get status of PSE control
1590 * @psec: PSE control pointer
1592 * @status: struct to store PSE status
1607 pcdev = psec->pcdev;
1608 ops = pcdev->ops;
1610 pi = &pcdev->pi[psec->id];
1611 mutex_lock(&pcdev->lock);
1612 if (pi->pw_d) {
1613 status->pw_d_id = pi->pw_d->id;
1614 if (pse_pw_d_is_sw_pw_control(pcdev, pi->pw_d)) {
1617 ret = ops->pi_get_admin_state(pcdev, psec->id,
1622 status->podl_admin_state = admin_state.podl_admin_state;
1623 status->c33_admin_state = admin_state.c33_admin_state;
1625 switch (pi->pw_d->budget_eval_strategy) {
1627 status->prio_max = pcdev->nr_lines - 1;
1628 status->prio = pi->prio;
1631 status->prio_max = pcdev->pis_prio_max;
1632 if (ops->pi_get_prio) {
1633 ret = ops->pi_get_prio(pcdev, psec->id);
1637 status->prio = ret;
1645 ret = ops->pi_get_pw_status(pcdev, psec->id, &pw_status);
1648 status->podl_pw_status = pw_status.podl_pw_status;
1649 status->c33_pw_status = pw_status.c33_pw_status;
1651 if (ops->pi_get_ext_state) {
1654 ret = ops->pi_get_ext_state(pcdev, psec->id,
1659 memcpy(&status->c33_ext_state_info,
1661 sizeof(status->c33_ext_state_info));
1664 if (ops->pi_get_pw_class) {
1665 ret = ops->pi_get_pw_class(pcdev, psec->id);
1669 status->c33_pw_class = ret;
1672 if (ops->pi_get_actual_pw) {
1673 ret = ops->pi_get_actual_pw(pcdev, psec->id);
1677 status->c33_actual_pw = ret;
1680 if (ops->pi_get_pw_limit) {
1681 ret = ops->pi_get_pw_limit(pcdev, psec->id);
1685 status->c33_avail_pw_limit = ret;
1688 if (ops->pi_get_pw_limit_ranges) {
1691 ret = ops->pi_get_pw_limit_ranges(pcdev, psec->id,
1696 status->c33_pw_limit_ranges =
1698 status->c33_pw_limit_nb_ranges = ret;
1701 mutex_unlock(&psec->pcdev->lock);
1714 switch (config->c33_admin_control) {
1721 if (psec->pcdev->pi[psec->id].admin_state_enabled &&
1722 !regulator_is_enabled(psec->ps)) {
1723 err = regulator_disable(psec->ps);
1727 if (!psec->pcdev->pi[psec->id].admin_state_enabled)
1728 err = regulator_enable(psec->ps);
1731 if (psec->pcdev->pi[psec->id].admin_state_enabled)
1732 err = regulator_disable(psec->ps);
1735 err = -EOPNOTSUPP;
1749 switch (config->podl_admin_control) {
1751 if (!psec->pcdev->pi[psec->id].admin_state_enabled)
1752 err = regulator_enable(psec->ps);
1755 if (psec->pcdev->pi[psec->id].admin_state_enabled)
1756 err = regulator_disable(psec->ps);
1759 err = -EOPNOTSUPP;
1766 * pse_ethtool_set_config - set PSE control configuration
1767 * @psec: PSE control pointer
1779 if (pse_has_c33(psec) && config->c33_admin_control) {
1785 if (pse_has_podl(psec) && config->podl_admin_control)
1793 * pse_pi_update_pw_budget - Update PSE power budget allocated with new
1795 * @pcdev: a pointer to the PSE controller device
1796 * @id: index of the PSE PI
1806 struct pse_pi *pi = &pcdev->pi[id];
1813 mutex_lock(&pcdev->lock);
1814 previous_pw_allocated = pi->pw_allocated_mW;
1815 pw_diff = pw_req - previous_pw_allocated;
1819 ret = regulator_request_power_budget(pi->pw_d->supply, pw_diff);
1828 regulator_free_power_budget(pi->pw_d->supply, -pw_diff);
1830 pi->pw_allocated_mW = pw_req;
1834 mutex_unlock(&pcdev->lock);
1839 * pse_ethtool_set_pw_limit - set PSE control power limit
1840 * @psec: PSE control pointer
1854 return -ERANGE;
1856 ret = regulator_get_voltage(psec->ps);
1859 "Can't calculate the current, PSE voltage read is 0");
1860 return -ERANGE;
1864 "Error reading PSE voltage");
1877 if (pse_pw_d_is_sw_pw_control(psec->pcdev,
1878 psec->pcdev->pi[psec->id].pw_d) &&
1879 psec->pcdev->pi[psec->id].admin_state_enabled &&
1880 psec->pcdev->pi[psec->id].isr_pd_detected) {
1881 ret = pse_pi_update_pw_budget(psec->pcdev, psec->id,
1888 ret = regulator_set_current_limit(psec->ps, 0, uA);
1890 pse_pi_update_pw_budget(psec->pcdev, psec->id,
1899 * pse_ethtool_set_prio - Set PSE PI priority according to the budget
1901 * @psec: PSE control pointer
1911 struct pse_controller_dev *pcdev = psec->pcdev;
1915 if (!pcdev->pi[psec->id].pw_d) {
1917 return -EOPNOTSUPP;
1923 mutex_lock(&pcdev->lock);
1924 switch (pcdev->pi[psec->id].pw_d->budget_eval_strategy) {
1926 if (prio >= pcdev->nr_lines) {
1929 prio, pcdev->nr_lines);
1930 ret = -ERANGE;
1934 pcdev->pi[psec->id].prio = prio;
1935 pse_pw_d_retry_power_delivery(pcdev, pcdev->pi[psec->id].pw_d);
1939 ops = psec->pcdev->ops;
1940 if (!ops->pi_set_prio) {
1942 "pse driver does not support setting port priority");
1943 ret = -EOPNOTSUPP;
1947 if (prio > pcdev->pis_prio_max) {
1950 prio, pcdev->pis_prio_max);
1951 ret = -ERANGE;
1955 ret = ops->pi_set_prio(pcdev, psec->id, prio);
1959 ret = -EOPNOTSUPP;
1963 mutex_unlock(&pcdev->lock);
1970 return psec->pcdev->types & ETHTOOL_PSE_PODL;
1976 return psec->pcdev->types & ETHTOOL_PSE_C33;