net/phy/nxp-c45-tja11xx-macsec.c

290 static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value)
369 	nxp_c45_macsec_write(phydev, MACSEC_EVER, reg);
474 	nxp_c45_macsec_write(phydev, sa_regs->npn, npn.lower);
475 	nxp_c45_macsec_write(phydev, sa_regs->xnpn, npn.upper);
484 	nxp_c45_macsec_write(phydev, sa_regs->lnpn, lnpn.lower);
485 	nxp_c45_macsec_write(phydev, sa_regs->lxnpn, lnpn.upper);
503 		nxp_c45_macsec_write(phydev, reg, value);
510 			nxp_c45_macsec_write(phydev, reg, value);
514 		nxp_c45_macsec_write(phydev, sa_regs->ssci, value);
517 	nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A);
523 	nxp_c45_macsec_write(phydev, sa->regs->ipis, 0);
524 	nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0);
525 	nxp_c45_macsec_write(phydev, sa->regs->ipos, 0);
527 	nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0);
528 	nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0);
543 	nxp_c45_macsec_write(phydev, sa->regs->opps, 0);
544 	nxp_c45_macsec_write(phydev, sa->regs->opes, 0);
563 	nxp_c45_macsec_write(phydev, sa_regs->cs, cfg);
586 	nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
594 	nxp_c45_macsec_write(phydev, sci_base_addr, lsci >> 32);
595 	nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci);
607 	nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id);
608 	nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id);
609 	nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id);
610 	nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id);
680 	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
691 	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg);
695 	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg);
699 	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
756 	nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
768 	nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0);
769 	nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0);
770 	nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0);
771 	nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0);
772 	nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0);
773 	nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0);
786 	nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);
810 	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg);
831 		nxp_c45_macsec_write(phydev, MACSEC_RPW,
857 	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg);
870 	nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0);
871 	nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0);
873 	nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0);
874 	nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0);
876 	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0);
877 	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0);
878 	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0);
881 		nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0);
882 		nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0);
891 	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0);
892 	nxp_c45_macsec_write(phydev, MACSEC_RPW, 0);
907 	nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0);
908 	nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0);
909 	nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0);
921 	nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);
1617 	ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN |
1622 	ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL,
1627 	ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN);
1631 	ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD);
1636 	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE);
1640 	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP);
1644 	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK);
1648 	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN);
1725 		nxp_c45_macsec_write(phydev, MACSEC_EVR,