Lines Matching refs:clock
6 static int mchp_rds_phy_read_mmd(struct mchp_rds_ptp_clock *clock,
9 struct phy_device *phydev = clock->phydev;
12 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
13 BASE_CLK(clock)));
15 return phy_read_mmd(phydev, PTP_MMD(clock), addr);
18 static int mchp_rds_phy_write_mmd(struct mchp_rds_ptp_clock *clock,
22 struct phy_device *phydev = clock->phydev;
25 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
26 BASE_CLK(clock)));
28 return phy_write_mmd(phydev, PTP_MMD(clock), addr, val);
31 static int mchp_rds_phy_modify_mmd(struct mchp_rds_ptp_clock *clock,
35 struct phy_device *phydev = clock->phydev;
38 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
39 BASE_CLK(clock)));
41 return phy_modify_mmd(phydev, PTP_MMD(clock), addr, mask, val);
44 static int mchp_rds_phy_set_bits_mmd(struct mchp_rds_ptp_clock *clock,
48 struct phy_device *phydev = clock->phydev;
51 addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
52 BASE_CLK(clock)));
54 return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val);
105 static int mchp_general_event_config(struct mchp_rds_ptp_clock *clock,
110 general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
120 return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
124 static int mchp_set_clock_reload(struct mchp_rds_ptp_clock *clock,
129 rc = mchp_rds_phy_write_mmd(clock,
136 rc = mchp_rds_phy_write_mmd(clock,
143 rc = mchp_rds_phy_write_mmd(clock,
150 return mchp_rds_phy_write_mmd(clock,
156 static int mchp_set_clock_target(struct mchp_rds_ptp_clock *clock,
162 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_LO,
168 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_HI,
174 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_LO,
180 return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_HI,
185 static int mchp_rds_ptp_perout_off(struct mchp_rds_ptp_clock *clock)
191 rc = mchp_set_clock_target(clock, 0xFFFFFFFF, 0);
195 general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
198 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
203 clock->mchp_rds_ptp_event = -1;
208 static bool mchp_get_event(struct mchp_rds_ptp_clock *clock, int pin)
210 if (clock->mchp_rds_ptp_event < 0 && pin == clock->event_pin) {
211 clock->mchp_rds_ptp_event = pin;
221 struct mchp_rds_ptp_clock *clock = container_of(ptpci,
224 struct phy_device *phydev = clock->phydev;
227 event_pin = ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
229 if (event_pin != clock->event_pin)
233 ret = mchp_rds_ptp_perout_off(clock);
237 if (!mchp_get_event(clock, event_pin))
245 ret = mchp_general_event_config(clock, pulsewidth);
249 ret = mchp_set_clock_target(clock, perout->start.sec,
254 return mchp_set_clock_reload(clock, perout->period.sec,
272 struct mchp_rds_ptp_clock *clock = container_of(ptpci,
276 if (!(pin == clock->event_pin && chan == 0))
290 static int mchp_rds_ptp_flush_fifo(struct mchp_rds_ptp_clock *clock,
296 skb_queue_purge(&clock->tx_queue);
298 skb_queue_purge(&clock->rx_queue);
301 rc = mchp_rds_phy_read_mmd(clock,
309 return mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_INT_STS,
313 static int mchp_rds_ptp_config_intr(struct mchp_rds_ptp_clock *clock,
317 return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_INT_EN,
325 struct mchp_rds_ptp_clock *clock = container_of(mii_ts,
329 switch (clock->hwts_tx_type) {
338 skb_queue_tail(&clock->tx_queue, skb);
368 static bool mchp_rds_ptp_match_skb(struct mchp_rds_ptp_clock *clock,
377 spin_lock_irqsave(&clock->rx_queue.lock, flags);
378 skb_queue_walk_safe(&clock->rx_queue, skb, skb_tmp) {
385 __skb_unlink(skb, &clock->rx_queue);
390 spin_unlock_irqrestore(&clock->rx_queue.lock, flags);
401 static void mchp_rds_ptp_match_rx_ts(struct mchp_rds_ptp_clock *clock,
409 if (!mchp_rds_ptp_match_skb(clock, rx_ts)) {
410 spin_lock_irqsave(&clock->rx_ts_lock, flags);
411 list_add(&rx_ts->list, &clock->rx_ts_list);
412 spin_unlock_irqrestore(&clock->rx_ts_lock, flags);
418 static void mchp_rds_ptp_match_rx_skb(struct mchp_rds_ptp_clock *clock,
430 spin_lock_irqsave(&clock->rx_ts_lock, flags);
431 list_for_each_entry_safe(rx_ts, tmp, &clock->rx_ts_list, list) {
444 spin_unlock_irqrestore(&clock->rx_ts_lock, flags);
450 skb_queue_tail(&clock->rx_queue, skb);
457 struct mchp_rds_ptp_clock *clock = container_of(mii_ts,
461 if (clock->rx_filter == HWTSTAMP_FILTER_NONE ||
465 if ((type & clock->version) == 0 || (type & clock->layer) == 0)
474 mchp_rds_ptp_match_rx_skb(clock, skb);
483 struct mchp_rds_ptp_clock *clock =
491 clock->hwts_tx_type = config->tx_type;
492 clock->rx_filter = config->rx_filter;
496 clock->layer = 0;
497 clock->version = 0;
502 clock->layer = PTP_CLASS_L4;
503 clock->version = PTP_CLASS_V2;
508 clock->layer = PTP_CLASS_L2;
509 clock->version = PTP_CLASS_V2;
514 clock->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
515 clock->version = PTP_CLASS_V2;
524 if (clock->layer & PTP_CLASS_L2) {
528 if (clock->layer & PTP_CLASS_L4) {
534 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_PARSE_CONFIG,
539 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_PARSE_CONFIG,
544 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_TIMESTAMP_EN,
550 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_TIMESTAMP_EN,
556 if (clock->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
558 rc = mchp_rds_phy_modify_mmd(clock, MCHP_RDS_PTP_TX_MOD,
563 rc = mchp_rds_phy_modify_mmd(clock, MCHP_RDS_PTP_TX_MOD,
572 spin_lock_irqsave(&clock->rx_ts_lock, flags);
573 list_for_each_entry_safe(rx_ts, tmp, &clock->rx_ts_list, list) {
577 spin_unlock_irqrestore(&clock->rx_ts_lock, flags);
579 rc = mchp_rds_ptp_flush_fifo(clock, MCHP_RDS_PTP_INGRESS_FIFO);
583 rc = mchp_rds_ptp_flush_fifo(clock, MCHP_RDS_PTP_EGRESS_FIFO);
588 rc = mchp_rds_ptp_config_intr(clock,
597 struct mchp_rds_ptp_clock *clock = container_of(mii_ts,
601 info->phc_index = ptp_clock_index(clock->ptp_clock);
620 struct mchp_rds_ptp_clock *clock = container_of(info,
672 mutex_lock(&clock->ptp_lock);
676 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_STEP_ADJ_LO,
681 rc = mchp_rds_phy_set_bits_mmd(clock, MCHP_RDS_PTP_STEP_ADJ_HI,
690 rc = mchp_rds_phy_set_bits_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
698 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_STEP_ADJ_LO,
704 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_STEP_ADJ_HI,
710 rc = mchp_rds_phy_set_bits_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
715 mutex_unlock(&clock->ptp_lock);
717 mutex_lock(&clock->ptp_lock);
722 if (clock->mchp_rds_ptp_event >= 0)
723 mchp_set_clock_target(clock,
726 mutex_unlock(&clock->ptp_lock);
734 struct mchp_rds_ptp_clock *clock = container_of(info,
759 mutex_lock(&clock->ptp_lock);
760 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_RATE_ADJ_HI,
765 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_RATE_ADJ_LO,
770 mutex_unlock(&clock->ptp_lock);
778 struct mchp_rds_ptp_clock *clock = container_of(info,
785 mutex_lock(&clock->ptp_lock);
789 rc = mchp_rds_phy_set_bits_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
795 /* Get LTC clock values */
796 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_LTC_READ_SEC_HI,
802 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_LTC_READ_SEC_MID,
809 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_LTC_READ_SEC_LO,
815 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_LTC_READ_NS_HI,
822 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_LTC_READ_NS_LO,
833 mutex_unlock(&clock->ptp_lock);
841 struct mchp_rds_ptp_clock *clock = container_of(info,
846 mutex_lock(&clock->ptp_lock);
847 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_SEC_LO,
853 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_SEC_MID,
859 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_SEC_HI,
865 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_NS_LO,
871 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LTC_NS_HI,
880 rc = mchp_rds_phy_set_bits_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
886 mutex_unlock(&clock->ptp_lock);
909 static void mchp_rds_ptp_match_tx_skb(struct mchp_rds_ptp_clock *clock,
918 spin_lock_irqsave(&clock->tx_queue.lock, flags);
919 skb_queue_walk_safe(&clock->tx_queue, skb, skb_tmp) {
926 __skb_unlink(skb, &clock->tx_queue);
930 spin_unlock_irqrestore(&clock->tx_queue.lock, flags);
939 *mchp_rds_ptp_get_rx_ts(struct mchp_rds_ptp_clock *clock)
941 struct phy_device *phydev = clock->phydev;
946 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_RX_INGRESS_NS_HI,
956 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_RX_INGRESS_NS_LO,
962 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_RX_INGRESS_SEC_HI,
968 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_RX_INGRESS_SEC_LO,
974 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_RX_MSG_HDR2,
991 static void mchp_rds_ptp_process_rx_ts(struct mchp_rds_ptp_clock *clock)
998 rx_ts = mchp_rds_ptp_get_rx_ts(clock);
1000 mchp_rds_ptp_match_rx_ts(clock, rx_ts);
1002 caps = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_CAP_INFO,
1009 static bool mchp_rds_ptp_get_tx_ts(struct mchp_rds_ptp_clock *clock,
1014 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_TX_EGRESS_NS_HI,
1022 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_TX_EGRESS_NS_LO,
1028 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_TX_EGRESS_SEC_HI,
1034 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_TX_EGRESS_SEC_LO,
1040 rc = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_TX_MSG_HDR2,
1050 static void mchp_rds_ptp_process_tx_ts(struct mchp_rds_ptp_clock *clock)
1058 if (mchp_rds_ptp_get_tx_ts(clock, &sec, &nsec, &seq))
1059 mchp_rds_ptp_match_tx_skb(clock, sec, nsec, seq);
1061 caps = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_CAP_INFO,
1068 int mchp_rds_ptp_top_config_intr(struct mchp_rds_ptp_clock *clock,
1072 return phy_clear_bits_mmd(clock->phydev, PTP_MMD(clock), reg,
1075 return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg,
1080 irqreturn_t mchp_rds_ptp_handle_interrupt(struct mchp_rds_ptp_clock *clock)
1085 if (!clock)
1089 irq_sts = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_INT_STS,
1095 mchp_rds_ptp_process_rx_ts(clock);
1098 mchp_rds_ptp_process_tx_ts(clock);
1101 mchp_rds_ptp_flush_fifo(clock,
1105 mchp_rds_ptp_flush_fifo(clock,
1116 static int mchp_rds_ptp_init(struct mchp_rds_ptp_clock *clock)
1121 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
1128 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TSU_GEN_CONFIG,
1134 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TSU_HARD_RESET,
1141 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_LATENCY_CORRECTION_CTL,
1148 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_OP_MODE,
1154 /* Reference clock configuration */
1155 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_REF_CLK_CFG,
1162 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_PARSE_CONFIG,
1167 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_PARSE_CONFIG,
1172 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_PARSE_L2_ADDR_EN,
1177 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_PARSE_L2_ADDR_EN,
1182 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_PARSE_IPV4_ADDR_EN,
1187 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_PARSE_IPV4_ADDR_EN,
1192 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_RX_VERSION,
1199 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TX_VERSION,
1207 rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_TSU_GEN_CONFIG,
1214 return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CMD_CTL,
1223 struct mchp_rds_ptp_clock *clock;
1226 clock = devm_kzalloc(&phydev->mdio.dev, sizeof(*clock), GFP_KERNEL);
1227 if (!clock)
1230 clock->port_base_addr = port_base_addr;
1231 clock->clk_base_addr = clk_base_addr;
1232 clock->mmd = mmd;
1234 mutex_init(&clock->ptp_lock);
1235 clock->pin_config = devm_kmalloc_array(&phydev->mdio.dev,
1237 sizeof(*clock->pin_config),
1239 if (!clock->pin_config)
1243 struct ptp_pin_desc *p = &clock->pin_config[i];
1250 /* Register PTP clock */
1251 clock->caps.owner = THIS_MODULE;
1252 snprintf(clock->caps.name, 30, "%s", phydev->drv->name);
1253 clock->caps.max_adj = MCHP_RDS_PTP_MAX_ADJ;
1254 clock->caps.n_ext_ts = 0;
1255 clock->caps.pps = 0;
1256 clock->caps.n_pins = MCHP_RDS_PTP_N_PIN;
1257 clock->caps.n_per_out = MCHP_RDS_PTP_N_PEROUT;
1258 clock->caps.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE;
1259 clock->caps.pin_config = clock->pin_config;
1260 clock->caps.adjfine = mchp_rds_ptp_ltc_adjfine;
1261 clock->caps.adjtime = mchp_rds_ptp_ltc_adjtime;
1262 clock->caps.gettime64 = mchp_rds_ptp_ltc_gettime64;
1263 clock->caps.settime64 = mchp_rds_ptp_ltc_settime64;
1264 clock->caps.enable = mchp_rds_ptpci_enable;
1265 clock->caps.verify = mchp_rds_ptpci_verify;
1266 clock->caps.getcrosststamp = NULL;
1267 clock->ptp_clock = ptp_clock_register(&clock->caps,
1269 if (IS_ERR(clock->ptp_clock))
1273 if (!clock->ptp_clock)
1277 skb_queue_head_init(&clock->tx_queue);
1278 skb_queue_head_init(&clock->rx_queue);
1279 INIT_LIST_HEAD(&clock->rx_ts_list);
1280 spin_lock_init(&clock->rx_ts_lock);
1282 clock->mii_ts.rxtstamp = mchp_rds_ptp_rxtstamp;
1283 clock->mii_ts.txtstamp = mchp_rds_ptp_txtstamp;
1284 clock->mii_ts.hwtstamp = mchp_rds_ptp_hwtstamp;
1285 clock->mii_ts.ts_info = mchp_rds_ptp_ts_info;
1287 phydev->mii_ts = &clock->mii_ts;
1289 clock->mchp_rds_ptp_event = -1;
1294 clock->phydev = phydev;
1296 rc = mchp_rds_ptp_init(clock);
1300 return clock;