Lines Matching defs:rrpriv
91 struct rr_private *rrpriv;
106 rrpriv = netdev_priv(dev);
116 rrpriv->pci_dev = pdev;
118 spin_lock_init(&rrpriv->lock);
146 rrpriv->regs = pci_iomap(pdev, 0, 0x1000);
147 if (!rrpriv->regs) {
156 rrpriv->tx_ring = tmpptr;
157 rrpriv->tx_ring_dma = ring_dma;
166 rrpriv->rx_ring = tmpptr;
167 rrpriv->rx_ring_dma = ring_dma;
176 rrpriv->evt_ring = tmpptr;
177 rrpriv->evt_ring_dma = ring_dma;
188 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
189 &rrpriv->regs->HostCtrl);
203 if (rrpriv->evt_ring)
204 dma_free_coherent(&pdev->dev, EVT_RING_SIZE, rrpriv->evt_ring,
205 rrpriv->evt_ring_dma);
206 if (rrpriv->rx_ring)
207 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, rrpriv->rx_ring,
208 rrpriv->rx_ring_dma);
209 if (rrpriv->tx_ring)
210 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, rrpriv->tx_ring,
211 rrpriv->tx_ring_dma);
212 if (rrpriv->regs)
213 pci_iounmap(pdev, rrpriv->regs);
252 static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
257 regs = rrpriv->regs;
270 idx = rrpriv->info->cmd_ctrl.pi;
276 rrpriv->info->cmd_ctrl.pi = idx;
290 struct rr_private *rrpriv;
295 rrpriv = netdev_priv(dev);
296 regs = rrpriv->regs;
367 rrpriv->info->evt_ctrl.pi = 0;
378 start_pc = rr_read_eeprom_word(rrpriv,
400 static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
405 struct rr_regs __iomem *regs = rrpriv->regs;
435 static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
440 if ((rr_read_eeprom(rrpriv, offset,
452 static unsigned int write_eeprom(struct rr_private *rrpriv,
457 struct rr_regs __iomem *regs = rrpriv->regs;
507 struct rr_private *rrpriv;
511 rrpriv = netdev_priv(dev);
512 regs = rrpriv->regs;
515 rrpriv->fw_rev = rev;
543 htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
545 htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
550 sram_size = rr_read_eeprom_word(rrpriv, 8);
559 struct rr_private *rrpriv;
567 rrpriv = netdev_priv(dev);
568 regs = rrpriv->regs;
570 spin_lock_irqsave(&rrpriv->lock, flags);
579 spin_unlock_irqrestore(&rrpriv->lock, flags);
584 set_rxaddr(regs, rrpriv->rx_ctrl_dma);
585 set_infoaddr(regs, rrpriv->info_dma);
587 rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
588 rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
589 rrpriv->info->evt_ctrl.mode = 0;
590 rrpriv->info->evt_ctrl.pi = 0;
591 set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
593 rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
594 rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
595 rrpriv->info->cmd_ctrl.mode = 0;
596 rrpriv->info->cmd_ctrl.pi = 15;
603 rrpriv->tx_ring[i].size = 0;
604 set_rraddr(&rrpriv->tx_ring[i].addr, 0);
605 rrpriv->tx_skbuff[i] = NULL;
607 rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
608 rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
609 rrpriv->info->tx_ctrl.mode = 0;
610 rrpriv->info->tx_ctrl.pi = 0;
611 set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
619 rrpriv->tx_full = 0;
620 rrpriv->cur_rx = 0;
621 rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
635 rrpriv->fw_running = 0;
642 spin_unlock_irqrestore(&rrpriv->lock, flags);
648 rrpriv->rx_ring[i].mode = 0;
656 rrpriv->rx_skbuff[i] = skb;
657 addr = dma_map_single(&rrpriv->pci_dev->dev, skb->data,
666 set_rraddr(&rrpriv->rx_ring[i].addr, addr);
667 rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
670 rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
671 rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
672 rrpriv->rx_ctrl[4].mode = 8;
673 rrpriv->rx_ctrl[4].pi = 0;
675 set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
686 rr_issue_cmd(rrpriv, &cmd);
692 while (time_before(jiffies, myjif) && !rrpriv->fw_running)
705 struct sk_buff *skb = rrpriv->rx_skbuff[i];
708 dma_unmap_single(&rrpriv->pci_dev->dev,
709 rrpriv->rx_ring[i].addr.addrlo,
712 rrpriv->rx_ring[i].size = 0;
713 set_rraddr(&rrpriv->rx_ring[i].addr, 0);
715 rrpriv->rx_skbuff[i] = NULL;
729 struct rr_private *rrpriv;
733 rrpriv = netdev_priv(dev);
734 regs = rrpriv->regs;
737 switch (rrpriv->evt_ring[eidx].code){
743 rrpriv->fw_running = 1;
910 u16 index = rrpriv->evt_ring[eidx].index;
913 rrpriv->rx_ring[index].mode |=
919 dev->name, rrpriv->evt_ring[eidx].code);
924 rrpriv->info->evt_ctrl.pi = eidx;
932 struct rr_private *rrpriv = netdev_priv(dev);
933 struct rr_regs __iomem *regs = rrpriv->regs;
939 desc = &(rrpriv->rx_ring[index]);
945 if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
953 rx_skb = rrpriv->rx_skbuff[index];
962 dma_sync_single_for_cpu(&rrpriv->pci_dev->dev,
970 dma_sync_single_for_device(&rrpriv->pci_dev->dev,
983 dma_unmap_single(&rrpriv->pci_dev->dev,
989 rrpriv->rx_skbuff[index] = newskb;
990 addr = dma_map_single(&rrpriv->pci_dev->dev,
1019 rrpriv->cur_rx = index;
1026 struct rr_private *rrpriv;
1031 rrpriv = netdev_priv(dev);
1032 regs = rrpriv->regs;
1037 spin_lock(&rrpriv->lock);
1046 prodidx, rrpriv->info->evt_ctrl.pi);
1054 eidx = rrpriv->info->evt_ctrl.pi;
1058 rxindex = rrpriv->cur_rx;
1062 txcon = rrpriv->dirty_tx;
1068 if(rrpriv->tx_skbuff[txcon]){
1072 desc = &(rrpriv->tx_ring[txcon]);
1073 skb = rrpriv->tx_skbuff[txcon];
1078 dma_unmap_single(&rrpriv->pci_dev->dev,
1083 rrpriv->tx_skbuff[txcon] = NULL;
1085 set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
1092 rrpriv->dirty_tx = txcon;
1093 if (rrpriv->tx_full && rr_if_busy(dev) &&
1094 (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
1095 != rrpriv->dirty_tx)){
1096 rrpriv->tx_full = 0;
1105 spin_unlock(&rrpriv->lock);
1109 static inline void rr_raz_tx(struct rr_private *rrpriv,
1115 struct sk_buff *skb = rrpriv->tx_skbuff[i];
1118 struct tx_desc *desc = &(rrpriv->tx_ring[i]);
1120 dma_unmap_single(&rrpriv->pci_dev->dev,
1126 rrpriv->tx_skbuff[i] = NULL;
1132 static inline void rr_raz_rx(struct rr_private *rrpriv,
1138 struct sk_buff *skb = rrpriv->rx_skbuff[i];
1141 struct rx_desc *desc = &(rrpriv->rx_ring[i]);
1143 dma_unmap_single(&rrpriv->pci_dev->dev,
1150 rrpriv->rx_skbuff[i] = NULL;
1157 struct rr_private *rrpriv = timer_container_of(rrpriv, t, timer);
1158 struct net_device *dev = pci_get_drvdata(rrpriv->pci_dev);
1159 struct rr_regs __iomem *regs = rrpriv->regs;
1164 memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
1165 memset(rrpriv->info, 0, sizeof(struct rr_info));
1168 rr_raz_tx(rrpriv, dev);
1169 rr_raz_rx(rrpriv, dev);
1172 spin_lock_irqsave(&rrpriv->lock, flags);
1175 spin_unlock_irqrestore(&rrpriv->lock, flags);
1178 rrpriv->timer.expires = RUN_AT(5*HZ);
1179 add_timer(&rrpriv->timer);
1185 struct rr_private *rrpriv = netdev_priv(dev);
1186 struct pci_dev *pdev = rrpriv->pci_dev;
1192 regs = rrpriv->regs;
1194 if (rrpriv->fw_rev < 0x00020000) {
1201 rrpriv->rx_ctrl = dma_alloc_coherent(&pdev->dev,
1204 if (!rrpriv->rx_ctrl) {
1208 rrpriv->rx_ctrl_dma = dma_addr;
1210 rrpriv->info = dma_alloc_coherent(&pdev->dev, sizeof(struct rr_info),
1212 if (!rrpriv->info) {
1216 rrpriv->info_dma = dma_addr;
1219 spin_lock_irqsave(&rrpriv->lock, flags);
1222 spin_unlock_irqrestore(&rrpriv->lock, flags);
1236 timer_setup(&rrpriv->timer, rr_timer, 0);
1237 rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
1238 add_timer(&rrpriv->timer);
1245 spin_lock_irqsave(&rrpriv->lock, flags);
1247 spin_unlock_irqrestore(&rrpriv->lock, flags);
1249 if (rrpriv->info) {
1251 rrpriv->info, rrpriv->info_dma);
1252 rrpriv->info = NULL;
1254 if (rrpriv->rx_ctrl) {
1256 rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1257 rrpriv->rx_ctrl = NULL;
1268 struct rr_private *rrpriv;
1274 rrpriv = netdev_priv(dev);
1275 regs = rrpriv->regs;
1282 rrpriv->info->tx_ctrl.pi);
1287 cons = rrpriv->dirty_tx;
1291 if (rrpriv->tx_skbuff[index]){
1292 len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
1293 printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
1297 printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
1302 if (rrpriv->tx_skbuff[cons]){
1303 len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
1304 printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
1306 rrpriv->tx_ring[cons].mode,
1307 rrpriv->tx_ring[cons].size,
1308 (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
1309 rrpriv->tx_skbuff[cons]->data,
1310 (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
1314 printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
1322 rrpriv->tx_ring[i].mode,
1323 rrpriv->tx_ring[i].size,
1324 (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
1331 struct rr_private *rrpriv = netdev_priv(dev);
1332 struct rr_regs __iomem *regs = rrpriv->regs;
1333 struct pci_dev *pdev = rrpriv->pci_dev;
1345 spin_lock_irqsave(&rrpriv->lock, flags);
1357 rrpriv->fw_running = 0;
1359 spin_unlock_irqrestore(&rrpriv->lock, flags);
1360 timer_delete_sync(&rrpriv->timer);
1361 spin_lock_irqsave(&rrpriv->lock, flags);
1372 rrpriv->info->tx_ctrl.entries = 0;
1373 rrpriv->info->cmd_ctrl.pi = 0;
1374 rrpriv->info->evt_ctrl.pi = 0;
1375 rrpriv->rx_ctrl[4].entries = 0;
1377 rr_raz_tx(rrpriv, dev);
1378 rr_raz_rx(rrpriv, dev);
1381 rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1382 rrpriv->rx_ctrl = NULL;
1384 dma_free_coherent(&pdev->dev, sizeof(struct rr_info), rrpriv->info,
1385 rrpriv->info_dma);
1386 rrpriv->info = NULL;
1388 spin_unlock_irqrestore(&rrpriv->lock, flags);
1398 struct rr_private *rrpriv = netdev_priv(dev);
1399 struct rr_regs __iomem *regs = rrpriv->regs;
1438 spin_lock_irqsave(&rrpriv->lock, flags);
1440 txctrl = &rrpriv->info->tx_ctrl;
1444 rrpriv->tx_skbuff[index] = skb;
1445 set_rraddr(&rrpriv->tx_ring[index].addr,
1446 dma_map_single(&rrpriv->pci_dev->dev, skb->data, len + 8, DMA_TO_DEVICE));
1447 rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
1448 rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
1453 if (txctrl->pi == rrpriv->dirty_tx){
1454 rrpriv->tx_full = 1;
1458 spin_unlock_irqrestore(&rrpriv->lock, flags);
1473 struct rr_private *rrpriv;
1480 rrpriv = netdev_priv(dev);
1481 regs = rrpriv->regs;
1506 sram_size = rr_read_eeprom_word(rrpriv, 8);
1517 eptr = rr_read_eeprom_word(rrpriv,
1521 p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
1523 p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
1531 revision = rr_read_eeprom_word(rrpriv,
1540 nr_seg = rr_read_eeprom_word(rrpriv, eptr);
1547 sptr = rr_read_eeprom_word(rrpriv, eptr);
1549 len = rr_read_eeprom_word(rrpriv, eptr);
1551 segptr = rr_read_eeprom_word(rrpriv, eptr);
1559 tmp = rr_read_eeprom_word(rrpriv, segptr);
1579 struct rr_private *rrpriv;
1585 rrpriv = netdev_priv(dev);
1597 if (rrpriv->fw_running){
1603 spin_lock_irqsave(&rrpriv->lock, flags);
1604 i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1605 spin_unlock_irqrestore(&rrpriv->lock, flags);
1634 if (rrpriv->fw_running){
1642 spin_lock_irqsave(&rrpriv->lock, flags);
1643 error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1648 i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
1649 spin_unlock_irqrestore(&rrpriv->lock, flags);