ethernet/xilinx/xilinx_axienet_mdio.c

25  * @lp:	Pointer to axienet local data structure.
31 static int axienet_mdio_wait_until_ready(struct axienet_local *lp)
35 	return readx_poll_timeout(axinet_ior_read_mcr, lp,
42  * @lp:	Pointer to axienet local data structure.
46 static void axienet_mdio_mdc_enable(struct axienet_local *lp)
48 	axienet_iow(lp, XAE_MDIO_MC_OFFSET,
49 		    ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));
54  * @lp:	Pointer to axienet local data structure.
58 static void axienet_mdio_mdc_disable(struct axienet_local *lp)
62 	mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
63 	axienet_iow(lp, XAE_MDIO_MC_OFFSET,
83 	struct axienet_local *lp = bus->priv;
85 	axienet_mdio_mdc_enable(lp);
87 	ret = axienet_mdio_wait_until_ready(lp);
89 		axienet_mdio_mdc_disable(lp);
93 	axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
101 	ret = axienet_mdio_wait_until_ready(lp);
103 		axienet_mdio_mdc_disable(lp);
107 	rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
109 	dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
112 	axienet_mdio_mdc_disable(lp);
133 	struct axienet_local *lp = bus->priv;
135 	dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
138 	axienet_mdio_mdc_enable(lp);
140 	ret = axienet_mdio_wait_until_ready(lp);
142 		axienet_mdio_mdc_disable(lp);
146 	axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
147 	axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
155 	ret = axienet_mdio_wait_until_ready(lp);
157 		axienet_mdio_mdc_disable(lp);
160 	axienet_mdio_mdc_disable(lp);
166  * @lp:		Pointer to axienet local data structure.
175 static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np)
182 	lp->mii_clk_div = 0;
184 	if (lp->axi_clk) {
185 		host_clock = clk_get_rate(lp->axi_clk);
194 			netdev_warn(lp->ndev, "Could not find CPU device node.\n");
200 				netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n");
205 		netdev_info(lp->ndev, "Setting assumed host clock to %u\n",
212 		netdev_info(lp->ndev, "Setting non-standard mdio bus frequency to %u Hz\n",
251 		netdev_warn(lp->ndev, "MDIO clock divisor overflow\n");
254 	lp->mii_clk_div = (u8)clk_div;
256 	netdev_dbg(lp->ndev,
258 		   lp->mii_clk_div, host_clock);
260 	axienet_mdio_mdc_enable(lp);
262 	ret = axienet_mdio_wait_until_ready(lp);
264 		axienet_mdio_mdc_disable(lp);
271  * @lp:		Pointer to axienet local data structure.
280 int axienet_mdio_setup(struct axienet_local *lp)
291 		 (unsigned long long)lp->regs_start);
293 	bus->priv = lp;
297 	bus->parent = lp->dev;
298 	lp->mii_bus = bus;
300 	mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio");
301 	ret = axienet_mdio_enable(lp, mdio_node);
308 	axienet_mdio_mdc_disable(lp);
312 	axienet_mdio_mdc_disable(lp);
316 	lp->mii_bus = NULL;
322  * @lp:		Pointer to axienet local data structure.
326 void axienet_mdio_teardown(struct axienet_local *lp)
328 	mdiobus_unregister(lp->mii_bus);
329 	mdiobus_free(lp->mii_bus);
330 	lp->mii_bus = NULL;