ethernet/xilinx/xilinx_axienet_main.c

781 	struct axidma_bd *cur_p;
787 		cur_p = &lp->tx_bd_v[(first_bd + i) % lp->tx_bd_num];
788 		status = cur_p->status;
798 		phys = desc_get_phys_addr(lp, cur_p);
800 				 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
803 		if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
804 			napi_consume_skb(cur_p->skb, budget);
808 		cur_p->app0 = 0;
809 		cur_p->app1 = 0;
810 		cur_p->app2 = 0;
811 		cur_p->app4 = 0;
812 		cur_p->skb = NULL;
815 		cur_p->cntrl = 0;
816 		cur_p->status = 0;
847 	struct axidma_bd *cur_p;
851 	cur_p = &lp->tx_bd_v[(READ_ONCE(lp->tx_bd_tail) + num_frag) %
853 	if (cur_p->cntrl)
1054 	struct axidma_bd *cur_p;
1060 	cur_p = &lp->tx_bd_v[orig_tail_ptr];
1076 			cur_p->app0 |= 2;
1081 			cur_p->app0 |= 1;
1082 			cur_p->app1 = (csum_start_off << 16) | csum_index_off;
1085 		cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
1097 	desc_set_phys_addr(lp, phys, cur_p);
1098 	cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
1103 		cur_p = &lp->tx_bd_v[new_tail_ptr];
1118 		desc_set_phys_addr(lp, phys, cur_p);
1119 		cur_p->cntrl = skb_frag_size(frag);
1122 	cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
1123 	cur_p->skb = skb;
1199 	struct axidma_bd *cur_p;
1203 	cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
1205 	while (packets < budget && (cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
1211 		skb = cur_p->skb;
1212 		cur_p->skb = NULL;
1220 			length = cur_p->app4 & 0x0000FFFF;
1222 			phys = desc_get_phys_addr(lp, cur_p);
1233 				csumstatus = (cur_p->app2 &
1240 				skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
1263 		desc_set_phys_addr(lp, phys, cur_p);
1265 		cur_p->cntrl = lp->max_frm_size;
1266 		cur_p->status = 0;
1267 		cur_p->skb = new_skb;
1276 		cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
2666 	struct axidma_bd *cur_p;
2685 		cur_p = &lp->tx_bd_v[i];
2686 		if (cur_p->cntrl) {
2687 			dma_addr_t addr = desc_get_phys_addr(lp, cur_p);
2690 					 (cur_p->cntrl &
2694 		if (cur_p->skb)
2695 			dev_kfree_skb_irq(cur_p->skb);
2696 		cur_p->phys = 0;
2697 		cur_p->phys_msb = 0;
2698 		cur_p->cntrl = 0;
2699 		cur_p->status = 0;
2700 		cur_p->app0 = 0;
2701 		cur_p->app1 = 0;
2702 		cur_p->app2 = 0;
2703 		cur_p->app3 = 0;
2704 		cur_p->app4 = 0;
2705 		cur_p->skb = NULL;
2709 		cur_p = &lp->rx_bd_v[i];
2710 		cur_p->status = 0;
2711 		cur_p->app0 = 0;
2712 		cur_p->app1 = 0;
2713 		cur_p->app2 = 0;
2714 		cur_p->app3 = 0;
2715 		cur_p->app4 = 0;