Lines Matching refs:reg_idx
1604 j = ring->reg_idx;
1612 u32 vlnctrl, i, vind, bits, reg_idx;
1633 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0));
1634 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx));
1636 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits);
1645 u32 i, vid, bits, vfta, vind, vlvf, reg_idx;
1659 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0));
1660 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx));
1662 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits);
1815 u8 reg_idx = ring->reg_idx;
1820 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1825 10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
1831 reg_idx);
1838 u8 reg_idx = ring->reg_idx;
1843 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx));
1849 reg_idx);
1857 u16 reg_idx = rx_ring->reg_idx;
1860 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1870 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
1877 u8 reg_idx = ring->reg_idx;
1882 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
1885 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32));
1886 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba));
1889 wr32(wx, WX_PX_TR_RP(reg_idx), 0);
1890 wr32(wx, WX_PX_TR_WP(reg_idx), 0);
1891 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx);
1909 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl);
1913 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx));
1915 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx);
1921 u16 reg_idx = ring->reg_idx;
1926 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
1929 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32));
1930 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba));
1938 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl);
1941 wr32(wx, WX_PX_RR_RP(reg_idx), 0);
1942 wr32(wx, WX_PX_RR_WP(reg_idx), 0);
1943 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx);
1956 wr32m(wx, WX_PX_RR_CFG(reg_idx),
2630 u16 reg_idx = ring->reg_idx;
2633 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
2636 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
2641 u16 reg_idx = ring->reg_idx;
2644 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));
2647 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);