Lines Matching full:mii

4   Provides Bus interface for MII registers
16 #include <linux/mii.h>
84 unsigned int mii_address = priv->hw->mii.addr;
85 unsigned int mii_data = priv->hw->mii.data;
93 /* Wait until any existing MII operation is complete */
100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
101 & priv->hw->mii.clk_csr_mask;
104 /* Wait until any existing MII operation is complete */
111 /* Set the MII address register to read */
115 /* Wait until any existing MII operation is complete */
122 /* Read the data from the MII data register */
167 unsigned int mii_address = priv->hw->mii.addr;
168 unsigned int mii_data = priv->hw->mii.data;
176 /* Wait until any existing MII operation is complete */
183 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
184 & priv->hw->mii.clk_csr_mask;
188 /* Wait until any existing MII operation is complete */
195 /* Set the MII address register to write */
199 /* Wait until any existing MII operation is complete */
246 unsigned int mii_address = priv->hw->mii.addr;
247 unsigned int mii_data = priv->hw->mii.data;
261 /* Read the data from the MII data register */
268 * @phyaddr: MII addr
269 * @phyreg: MII reg
270 * Description: it reads data from the MII register from within the phy device.
271 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
286 value |= (phyaddr << priv->hw->mii.addr_shift)
287 & priv->hw->mii.addr_mask;
288 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
289 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
290 & priv->hw->mii.clk_csr_mask;
304 * @phyaddr: MII addr
306 * @phyreg: MII reg
307 * Description: it reads data from the MII register from within the phy device.
308 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
326 value |= (phyaddr << priv->hw->mii.addr_shift)
327 & priv->hw->mii.addr_mask;
328 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
329 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
330 & priv->hw->mii.clk_csr_mask;
333 value &= ~priv->hw->mii.reg_mask;
334 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
347 unsigned int mii_address = priv->hw->mii.addr;
348 unsigned int mii_data = priv->hw->mii.data;
351 /* Wait until any existing MII operation is complete */
356 /* Set the MII address register to write */
360 /* Wait until any existing MII operation is complete */
368 * @phyaddr: MII addr
369 * @phyreg: MII reg
371 * Description: it writes the data into the MII register from within the device.
385 value |= (phyaddr << priv->hw->mii.addr_shift)
386 & priv->hw->mii.addr_mask;
387 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
389 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
390 & priv->hw->mii.clk_csr_mask;
406 * @phyaddr: MII addr
407 * @phyreg: MII reg
410 * Description: it writes the data into the MII register from within the device.
426 value |= (phyaddr << priv->hw->mii.addr_shift)
427 & priv->hw->mii.addr_mask;
428 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
430 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
431 & priv->hw->mii.clk_csr_mask;
435 value &= ~priv->hw->mii.reg_mask;
436 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
450 * Description: reset the MII bus
457 unsigned int mii_address = priv->hw->mii.addr;
518 xpcs = xpcs_create_mdiodev(priv->mii, addr);
552 * Description: it registers the MII bus
682 priv->mii = new_bus;
696 * Description: it unregisters the MII bus
702 if (!priv->mii)
705 mdiobus_unregister(priv->mii);
706 priv->mii->priv = NULL;
707 mdiobus_free(priv->mii);
708 priv->mii = NULL;