Lines Matching defs:ahw

16 	QLCWRX(adapter->ahw, QLC_83XX_VNIC_STATE, QLCNIC_DEV_NPAR_OPER);
25 	struct qlcnic_hardware_context *ahw = adapter->ahw;
32 	QLCWRX(adapter->ahw, QLC_83XX_VNIC_STATE, QLCNIC_DEV_NPAR_NON_OPER);
33 	ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER;
46 	struct qlcnic_hardware_context *ahw = adapter->ahw;
51 	id = ahw->pci_func;
52 	data = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
56 	QLCWRX(adapter->ahw, QLC_83XX_DRV_OP_MODE, data);
66 	struct qlcnic_hardware_context *ahw = adapter->ahw;
68 	if (ahw->port_type == QLCNIC_XGBE) {
74 	} else if (ahw->port_type == QLCNIC_GBE) {
96 	struct qlcnic_hardware_context *ahw = adapter->ahw;
109 		for (i = 0; i < ahw->total_nic_func; i++, npar++) {
117 			 ahw->max_pci_func, ahw->total_nic_func);
133 	ahw->msix_supported = qlcnic_use_msi_x ? 1 : 0;
138 		 ahw->fw_hal_version);
152 	adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
157 		 adapter->ahw->fw_hal_version);
173 	adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
177 		 adapter->ahw->fw_hal_version);
194 	struct qlcnic_hardware_context *ahw = adapter->ahw;
198 	op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
204 							 ahw->pci_func);
207 		ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
208 		ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
212 		ahw->op_mode = QLCNIC_PRIV_FUNC;
213 		ahw->idc.state_entry = qlcnic_83xx_idc_vnic_pf_entry;
217 		ahw->op_mode = QLCNIC_MGMT_FUNC;
218 		ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
226 	if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) {
235 	ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER;
236 	ahw->idc.vnic_wait_limit = QLCNIC_DEV_NPAR_OPER_TIMEO;
243 	struct qlcnic_hardware_context *ahw = adapter->ahw;
244 	struct qlc_83xx_idc *idc = &ahw->idc;
247 	state = QLCRDX(ahw, QLC_83XX_VNIC_STATE);
251 		state = QLCRDX(ahw, QLC_83XX_VNIC_STATE);