Lines Matching full:x1

322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK		0x1
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
326 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
342 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
344 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
346 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
435 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
437 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
439 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
441 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
443 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
445 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
447 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
449 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
452 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
454 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
456 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
458 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
460 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
462 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
464 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
466 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
520 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
522 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
525 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
527 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
529 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
531 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
533 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
535 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
537 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
539 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
542 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
544 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
546 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
548 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
550 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
552 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
554 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
556 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
559 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
561 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
563 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
565 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
567 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
569 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
571 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
573 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
576 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
578 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
580 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
582 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
584 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
586 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
588 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
590 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
593 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
595 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
597 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
599 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
601 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
603 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
605 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
607 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
610 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
612 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
614 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
616 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
618 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
620 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
622 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
624 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
627 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
629 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
631 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
633 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
635 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
637 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
698 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
700 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
702 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
704 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
706 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
708 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
735 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
737 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
739 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
741 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
744 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
746 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
748 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
750 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
752 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
754 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
756 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
758 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
761 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
763 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
765 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
767 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
769 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
771 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
773 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
775 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
802 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
804 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
822 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
824 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
826 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
828 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
830 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
832 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
834 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
836 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
839 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
841 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
843 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
845 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
847 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
849 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
851 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
853 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
1038 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1492 #define DMAE_CMD_SRC_MASK 0x1
1496 #define DMAE_CMD_C_DST_MASK 0x1
1498 #define DMAE_CMD_CRC_RESET_MASK 0x1
1500 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1502 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1504 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1506 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1508 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1512 #define DMAE_CMD_RESERVED1_MASK 0x1
1524 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1526 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1549 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1606 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1608 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1617 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1619 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1621 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1623 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1625 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1627 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1629 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1631 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1643 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1645 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1654 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1656 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1658 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1660 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1662 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1664 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1666 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1668 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1693 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1695 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1697 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1699 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1701 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1703 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1705 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1723 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1727 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1746 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1753 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1759 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1772 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1785 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1787 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1789 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1791 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1793 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1795 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1812 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1814 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1816 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1818 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1820 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1822 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1824 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1826 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1833 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1835 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1837 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1839 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1841 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1843 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1845 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1847 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1849 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1858 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1868 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1879 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
2270 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2272 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2286 #define INIT_READ_OP_RESERVED_MASK 0x1
3219 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3221 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
3223 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
3225 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3227 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
3229 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
3231 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
3233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
3236 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
3238 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
3240 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
3242 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
3244 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
3246 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
3248 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3250 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3304 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3306 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3309 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3311 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3313 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3315 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3317 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3319 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3321 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3323 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3326 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3328 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
3330 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
3332 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
3334 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
3336 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
3338 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
3340 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
3343 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
3345 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
3347 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
3349 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
3351 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
3353 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
3355 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
3357 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
3360 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
3362 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
3364 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
3366 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3368 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3370 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3372 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
3374 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
3377 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
3379 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
3381 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
3383 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
3385 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
3387 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
3389 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
3391 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
3394 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
3396 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
3398 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
3400 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
3402 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
3404 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
3406 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
3408 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
3411 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
3413 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
3415 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
3417 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
3419 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
3421 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
3487 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3489 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3498 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3500 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
3502 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3504 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3506 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3508 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3510 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3512 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3531 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3533 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3535 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
3537 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
3539 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
3541 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
3568 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3570 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3572 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3574 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3577 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3579 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3581 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3583 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3585 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3587 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3589 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3591 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3594 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3596 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3598 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3600 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3602 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3604 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
3606 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3608 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3635 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3637 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3655 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
3657 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
3659 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3661 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3663 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
3665 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
3667 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3669 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3672 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3674 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3676 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3678 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3680 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3682 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3684 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3686 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3892 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
3894 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
3916 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
3918 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
3920 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
3922 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
3924 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
3926 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
3928 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
3930 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
3939 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
3941 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
3943 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
3945 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
3947 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
3949 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
3951 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
3979 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
3981 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
3983 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
3985 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
3987 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3989 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3991 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
4020 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4022 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4024 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4026 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4028 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4175 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4177 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4179 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4181 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4183 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4341 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
4343 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
4345 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
4347 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
4349 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
4351 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
4353 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
4355 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
4358 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
4360 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
4362 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
4364 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
4366 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
4368 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
4370 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
4372 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
4426 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
4428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
4431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
4433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
4435 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
4437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
4439 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
4441 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
4443 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
4445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
4448 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
4450 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
4452 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
4454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
4456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
4458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
4460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
4462 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
4465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
4467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
4469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
4471 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
4473 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
4475 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
4477 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
4479 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
4482 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
4484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
4486 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
4488 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
4490 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
4492 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
4494 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
4496 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
4499 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
4501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
4503 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
4505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
4507 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
4509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
4511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
4513 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
4516 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
4518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
4520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
4522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
4524 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
4526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
4528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
4530 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
4533 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
4535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
4537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
4539 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4541 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
4543 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
4570 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4572 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4581 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4583 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4585 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4587 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4589 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4591 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4593 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4595 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4607 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4609 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
4611 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
4613 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4615 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
4617 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
4619 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
4621 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
4624 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
4626 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
4628 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
4630 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
4632 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4634 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4636 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4638 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4692 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
4694 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
4697 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
4699 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
4701 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
4703 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
4705 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
4707 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
4709 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
4711 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
4714 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
4716 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
4718 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
4720 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
4722 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
4724 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
4726 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4728 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4731 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4733 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4735 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4737 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
4739 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4741 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4743 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
4745 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
4748 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
4750 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
4752 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4754 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
4756 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
4758 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
4760 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4762 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
4765 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
4767 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
4769 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4771 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4773 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
4775 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
4777 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
4779 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
4782 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
4784 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
4786 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4788 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4790 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4792 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4794 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4796 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4799 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4801 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4803 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4805 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4807 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4809 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4826 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
4828 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
4830 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
4838 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
4840 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
4862 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
4864 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
4913 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
4915 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
4917 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
4919 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
4921 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
4923 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
4925 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
4927 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
4929 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
4931 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
4933 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
4935 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
4937 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
4939 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
4941 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
4943 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
4945 #define GFT_RAM_LINE_TTL_MASK 0x1
4947 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
4949 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
4951 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
4953 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
4955 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
4957 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
4959 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
4961 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
4963 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
4965 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
4967 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
4969 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
4971 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
4974 #define GFT_RAM_LINE_DSCP_MASK 0x1
4976 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
4978 #define GFT_RAM_LINE_DST_IP_MASK 0x1
4980 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
4982 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
4984 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
4986 #define GFT_RAM_LINE_VLAN_MASK 0x1
4988 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
4990 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
4992 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
5019 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5021 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5023 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5025 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5034 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5036 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5039 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5041 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5043 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5045 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5047 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5049 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5051 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5053 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5075 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5077 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5079 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5081 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5090 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5092 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5095 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5097 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5099 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5101 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5103 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5105 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5107 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5109 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5141 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5143 #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5157 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5159 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5161 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5163 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
5165 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5167 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5169 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5171 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5174 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
5176 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5178 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
5180 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5245 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5247 #define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5256 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5258 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1
5260 #define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5262 #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1
5264 #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5266 #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5268 #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5270 #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1
5289 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5291 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
5293 #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK 0x1
5295 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5297 #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK 0x1
5299 #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK 0x1
5301 #define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK 0x1
5303 #define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK 0x1
5306 #define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK 0x1
5308 #define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK 0x1
5310 #define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK 0x1
5312 #define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK 0x1
5314 #define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK 0x1
5316 #define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK 0x1
5318 #define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK 0x1
5320 #define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK 0x1
5374 #define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5376 #define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5379 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5381 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5383 #define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5385 #define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5387 #define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5389 #define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5391 #define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5393 #define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK 0x1
5396 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5398 #define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK 0x1
5400 #define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK 0x1
5402 #define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK 0x1
5404 #define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK 0x1
5406 #define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK 0x1
5408 #define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK 0x1
5410 #define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK 0x1
5413 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK 0x1
5415 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
5417 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5419 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
5421 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5423 #define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK 0x1
5425 #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5427 #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
5430 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
5432 #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5434 #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK 0x1
5436 #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5438 #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5440 #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5442 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5444 #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK 0x1
5447 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK 0x1
5449 #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK 0x1
5451 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5453 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5455 #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK 0x1
5457 #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK 0x1
5459 #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK 0x1
5461 #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK 0x1
5464 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK 0x1
5466 #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK 0x1
5468 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5470 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5472 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5474 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5476 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5478 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5481 #define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK 0x1
5483 #define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK 0x1
5485 #define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK 0x1
5487 #define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK 0x1
5489 #define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK 0x1
5491 #define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK 0x1
5546 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5548 #define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5550 #define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK 0x1
5552 #define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK 0x1
5554 #define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK 0x1
5556 #define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK 0x1
5583 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK 0x1
5585 #define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5587 #define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5589 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5592 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5594 #define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5596 #define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5598 #define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5600 #define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5602 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5604 #define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5606 #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5609 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5611 #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5613 #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5615 #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5617 #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5619 #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5621 #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5623 #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5643 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5645 #define USTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5663 #define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5665 #define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5667 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK 0x1
5669 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5671 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5673 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5675 #define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5677 #define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5680 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5682 #define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5684 #define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5686 #define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5688 #define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5690 #define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5692 #define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5694 #define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5824 #define TOE_RX_BD_START_MASK 0x1
5826 #define TOE_RX_BD_END_MASK 0x1
5828 #define TOE_RX_BD_NO_PUSH_MASK 0x1
5830 #define TOE_RX_BD_SPLIT_MASK 0x1
5937 #define TOE_TX_BD_PUSH_MASK 0x1
5939 #define TOE_TX_BD_NOTIFY_MASK 0x1
5941 #define TOE_TX_BD_LARGE_IO_MASK 0x1
5981 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK 0x1
5999 #define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK 0x1
6001 #define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
6010 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
6012 #define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
6014 #define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
6016 #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
6018 #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
6020 #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
6022 #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
6024 #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
6039 #define TOE_DB_DATA_BYPASS_EN_MASK 0x1
6041 #define TOE_DB_DATA_RESERVED_MASK 0x1
6083 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6147 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK 0x1
6149 #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK 0x1
6151 #define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK 0x1
6196 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6198 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6200 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6202 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6204 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6206 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6208 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6210 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6212 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6222 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6224 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6252 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6254 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6256 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6277 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
6279 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6328 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6330 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6332 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6334 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6337 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6339 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6359 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6361 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6363 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6365 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6367 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6369 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6372 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6374 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6376 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6378 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6380 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6382 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6384 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6386 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6404 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6406 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
6424 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6426 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6428 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6430 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6432 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6434 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6436 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6438 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6441 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6443 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6445 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6447 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6449 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6451 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6453 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6455 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6473 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6475 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6477 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6479 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6481 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6483 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6485 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
6487 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
6490 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
6492 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
6494 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
6496 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
6498 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
6500 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
6502 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
6504 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6558 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6560 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
6563 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6565 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
6567 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
6569 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6571 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6573 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6575 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6577 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6580 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6582 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
6584 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
6586 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
6588 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
6590 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
6592 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
6594 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
6597 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
6599 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
6601 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
6603 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
6605 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6607 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
6609 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6611 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6614 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6616 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6618 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6620 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6622 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6624 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6626 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6628 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
6631 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
6633 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
6635 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6637 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6639 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
6641 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
6643 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
6645 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
6648 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
6650 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
6652 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6654 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6656 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6658 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6660 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6662 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6665 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
6667 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
6671 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
6673 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6702 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6704 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6706 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6708 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
6710 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6712 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6739 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6741 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6743 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6745 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6748 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6750 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6752 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6754 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
6756 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6758 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6760 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6762 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6765 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6767 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6769 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6771 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6773 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6775 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6777 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6779 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
6865 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6867 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6871 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
6905 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
6907 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6909 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
6924 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6926 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6928 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6930 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6932 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6934 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6940 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
6942 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6944 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
6987 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1
7007 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7009 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7146 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7148 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7168 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK 0x1
7179 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7181 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7183 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7185 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7187 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7189 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7191 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7193 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7195 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7197 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7201 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7203 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
7205 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x1
7230 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7232 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7234 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7236 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7238 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7240 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7242 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7244 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7246 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7248 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7250 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7252 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
7278 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7280 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7295 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7310 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7329 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7331 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7389 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7391 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7402 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
7404 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
7406 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
7408 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
7410 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
7412 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
7414 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
7416 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
7419 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
7421 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
7423 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
7425 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
7427 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
7429 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
7431 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
7433 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
7487 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
7489 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
7492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
7494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
7496 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
7498 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
7500 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
7502 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
7504 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
7506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
7509 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
7511 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
7513 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
7515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
7517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
7519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
7521 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
7523 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
7526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
7528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
7530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
7532 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
7534 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
7536 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
7538 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
7540 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
7543 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
7545 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
7547 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
7549 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
7551 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
7553 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
7555 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
7557 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
7560 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
7562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
7564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
7566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
7568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
7570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
7572 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
7574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
7577 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
7579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
7581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
7583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
7585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
7587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
7589 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
7591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
7594 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
7596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
7600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
7602 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
7629 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
7631 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7640 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7642 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7644 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7646 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7648 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7650 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7652 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7654 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7666 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7668 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7677 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7679 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7681 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7683 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7685 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7687 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7689 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7691 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7703 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7705 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7714 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7716 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7718 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7720 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7722 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7724 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7726 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7728 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7740 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7742 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7744 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7746 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7748 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7750 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7777 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7779 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7781 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7783 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7786 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7788 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
7790 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7792 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7794 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7796 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7798 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7800 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7803 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7805 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7813 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7815 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7817 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7844 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7846 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7848 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7850 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7852 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7854 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7881 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7883 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7885 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7887 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7890 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7892 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7894 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7896 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7898 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7900 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7902 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7904 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7907 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7909 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7917 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7919 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7921 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7948 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7950 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7968 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7970 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7972 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7974 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7976 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7978 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7980 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7982 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7985 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7987 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7989 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7991 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7993 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7995 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7997 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7999 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8017 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8019 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8037 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8039 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8041 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8043 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8045 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8047 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8049 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8051 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8054 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8056 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8058 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8060 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8062 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8064 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8066 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8068 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8086 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8088 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8090 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8092 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8094 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8096 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8098 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8100 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8103 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8105 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8107 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8109 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8111 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8113 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8115 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8117 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8171 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8180 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8182 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8184 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8186 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8188 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8193 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8195 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8197 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8207 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8216 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8220 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8222 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8224 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8227 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8231 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8233 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8235 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8237 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8239 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8241 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8244 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8246 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8248 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8250 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8252 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8254 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8256 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8258 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8261 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8263 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8265 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8267 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8269 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8271 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8273 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8275 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8278 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8280 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8284 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8286 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8315 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8317 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8319 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8321 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8323 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8325 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8327 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8329 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8332 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8334 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8336 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8338 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8340 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8342 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8344 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8346 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8400 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8409 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8411 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8413 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8415 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8417 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8422 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8424 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8426 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8436 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8445 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8449 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8451 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8453 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8456 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8460 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8462 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8464 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8466 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8468 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8470 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8473 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8477 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8479 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8481 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8483 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8485 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8487 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8490 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8492 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8494 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8496 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8498 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8500 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8502 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8504 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8507 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8509 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8511 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8513 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8515 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8517 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8546 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8548 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8557 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8559 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8561 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8563 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8565 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8567 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8569 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8571 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8590 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8592 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8601 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8603 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8605 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8607 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8609 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8611 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8613 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8615 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8634 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8636 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8645 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8647 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8649 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8651 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8653 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8655 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8657 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8659 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8701 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8703 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8705 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8707 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8709 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8711 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8713 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8715 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8718 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8720 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8722 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8724 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8726 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8728 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8730 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8732 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8786 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8788 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8791 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8793 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8795 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8797 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8799 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8801 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8803 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8805 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8808 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8810 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8812 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8814 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8816 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8818 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8820 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8822 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8825 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8827 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8829 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8831 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8833 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8835 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
8837 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8839 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8842 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8844 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8846 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8848 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8850 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8852 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8854 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8856 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8859 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8861 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8863 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8865 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8867 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8869 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8871 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8873 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8876 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8878 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
8880 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8882 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8884 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8886 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8888 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8890 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8893 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8895 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8897 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8899 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8901 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8903 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8958 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8960 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
8962 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
8964 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
8966 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8968 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8995 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8997 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
8999 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9001 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9004 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9006 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9008 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9010 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9012 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9014 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9016 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9018 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9021 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9023 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9025 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9027 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9029 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9031 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9033 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9035 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9094 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9096 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9098 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9100 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9102 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9104 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9106 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9108 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9219 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9221 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9223 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9225 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9227 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9229 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9301 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9365 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9367 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9378 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9380 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9389 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9391 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9393 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9395 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9397 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9399 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9401 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9403 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9415 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9417 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9435 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9437 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9439 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9441 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9443 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9445 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9447 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9449 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9452 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9454 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9456 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9458 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9460 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9462 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9464 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9466 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9484 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9486 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9495 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9497 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9499 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9501 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9503 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9505 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9507 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9509 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9540 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9542 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9550 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9552 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9564 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9616 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9618 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9620 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9622 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9624 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
9645 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9647 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9649 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9680 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9682 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9684 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9686 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9704 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9706 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9708 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9710 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9712 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9714 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9716 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9718 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9721 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9723 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9725 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9727 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9729 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9731 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9733 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9735 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9789 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9791 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9794 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9796 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9798 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9800 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9802 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9804 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9806 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9808 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9811 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9813 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9815 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9817 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9819 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9821 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9823 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9825 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9828 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9830 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9832 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9834 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9836 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9838 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9840 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9842 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9845 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9847 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9849 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9851 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9853 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9855 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9857 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9859 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9862 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9864 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9866 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9868 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9870 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9872 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9874 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9876 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9879 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9881 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9883 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9885 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9887 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9889 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9891 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9893 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9896 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9898 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9900 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9902 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9904 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9906 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9951 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9953 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9955 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
9957 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
9959 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
9961 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
9988 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
9990 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9992 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9994 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
9997 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9999 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10001 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10003 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10005 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10007 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10009 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10011 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10014 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10016 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10018 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10020 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10022 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10024 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10026 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10028 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10038 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10040 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10058 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10060 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10062 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10064 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10066 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10068 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10070 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10072 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10075 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10077 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10079 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10081 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10083 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10085 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10087 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10089 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10109 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10111 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10135 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10137 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10146 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10148 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10150 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10152 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10154 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10156 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10158 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10160 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10174 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10176 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10276 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10278 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10287 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10289 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10291 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10293 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10295 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10297 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10299 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10301 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10337 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10339 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10341 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10343 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10345 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10347 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10349 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10351 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10354 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10356 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10358 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10360 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10362 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10364 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10366 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10368 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10422 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10424 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10427 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10429 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10431 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10433 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10435 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10437 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10439 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10441 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10444 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10446 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10448 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10450 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10452 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10454 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10456 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10458 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10461 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10463 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10465 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10467 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10469 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10471 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10473 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10475 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10478 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10480 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10482 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10484 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10486 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10488 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10490 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10492 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10495 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10497 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10499 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10501 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10503 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10505 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10507 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10509 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10512 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10514 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10516 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10518 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10520 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10522 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10524 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10526 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10529 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10531 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10533 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10535 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10537 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10539 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10594 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10596 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10598 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10600 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10602 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10604 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10631 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10633 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10635 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10637 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10640 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10642 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10644 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10646 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10648 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10650 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10652 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
10654 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10657 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10659 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10661 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10663 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10665 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10667 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10669 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10671 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10691 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10693 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10711 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10713 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10715 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10717 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10719 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10721 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10723 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10725 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10728 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10730 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10732 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10734 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10736 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10738 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10740 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10742 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10765 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10767 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10776 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10778 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10780 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10782 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10784 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10786 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10788 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10790 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10840 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10842 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10851 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10853 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10855 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10857 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10859 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10861 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10863 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10865 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1