Lines Matching defs:lif
39 static void ionic_link_status_check(struct ionic_lif *lif);
40 static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
41 static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
42 static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
44 static void ionic_txrx_deinit(struct ionic_lif *lif);
45 static int ionic_txrx_init(struct ionic_lif *lif);
46 static int ionic_start_queues(struct ionic_lif *lif);
47 static void ionic_stop_queues(struct ionic_lif *lif);
48 static void ionic_lif_queue_identify(struct ionic_lif *lif);
50 static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif);
60 struct ionic_lif *lif;
70 lif = q->lif;
71 new_coal = ionic_coal_usec_to_hw(lif->ionic, cur_moder.usec);
78 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
87 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
88 struct ionic_deferred *def = &lif->deferred;
105 ionic_lif_rx_mode(lif);
108 ionic_link_status_check(lif);
112 ionic_lif_handle_fw_up(lif);
114 ionic_lif_handle_fw_down(lif);
120 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1);
131 void ionic_lif_deferred_enqueue(struct ionic_lif *lif,
134 spin_lock_bh(&lif->deferred.lock);
135 list_add_tail(&work->list, &lif->deferred.list);
136 spin_unlock_bh(&lif->deferred.lock);
137 queue_work(lif->ionic->wq, &lif->deferred.work);
140 static void ionic_link_status_check(struct ionic_lif *lif)
142 struct net_device *netdev = lif->netdev;
146 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
150 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
151 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
155 link_status = le16_to_cpu(lif->info->status.link_status);
162 mutex_lock(&lif->queue_lock);
163 err = ionic_start_queues(lif);
167 set_bit(IONIC_LIF_F_BROKEN, lif->state);
168 netif_carrier_off(lif->netdev);
170 mutex_unlock(&lif->queue_lock);
174 ionic_port_identify(lif->ionic);
176 le32_to_cpu(lif->info->status.link_speed) / 1000);
181 lif->link_down_count++;
187 mutex_lock(&lif->queue_lock);
188 ionic_stop_queues(lif);
189 mutex_unlock(&lif->queue_lock);
193 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
196 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
201 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
207 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
212 ionic_lif_deferred_enqueue(lif, work);
214 ionic_link_status_check(lif);
227 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
230 struct device *dev = lif->ionic->dev;
234 if (lif->registered)
235 name = netdev_name(lif->netdev);
246 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
248 struct ionic *ionic = lif->ionic;
253 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
285 struct ionic_lif *lif = q->lif;
293 .lif_index = cpu_to_le16(lif->index),
301 idev = &lif->ionic->idev;
302 dev = lif->ionic->dev;
310 ret = ionic_adminq_post_wait(lif, &ctx);
327 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err)
340 netdev_err(lif->netdev, "%s: bad qcq\n", __func__);
347 struct ionic_dev *idev = &lif->ionic->idev;
349 if (lif->doorbell_wa)
366 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
369 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
372 return ionic_adminq_post_wait(lif, &ctx);
375 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
377 struct ionic_dev *idev = &lif->ionic->idev;
395 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
401 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
403 ionic_intr_free(lif->ionic, qcq->intr.index);
407 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
409 struct device *dev = lif->ionic->dev;
424 ionic_put_cmb(lif, qcq->cmb_pgid, qcq->cmb_order);
446 ionic_qcq_intr_free(lif, qcq);
451 void ionic_qcqs_free(struct ionic_lif *lif)
453 struct device *dev = lif->ionic->dev;
457 if (lif->notifyqcq) {
458 ionic_qcq_free(lif, lif->notifyqcq);
459 devm_kfree(dev, lif->notifyqcq);
460 lif->notifyqcq = NULL;
463 if (lif->adminqcq) {
464 spin_lock_irqsave(&lif->adminq_lock, irqflags);
465 adminqcq = READ_ONCE(lif->adminqcq);
466 lif->adminqcq = NULL;
467 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
469 ionic_qcq_free(lif, adminqcq);
474 if (lif->rxqcqs) {
475 devm_kfree(dev, lif->rxqstats);
476 lif->rxqstats = NULL;
477 devm_kfree(dev, lif->rxqcqs);
478 lif->rxqcqs = NULL;
481 if (lif->txqcqs) {
482 devm_kfree(dev, lif->txqstats);
483 lif->txqstats = NULL;
484 devm_kfree(dev, lif->txqcqs);
485 lif->txqcqs = NULL;
496 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
506 err = ionic_intr_alloc(lif, &qcq->intr);
508 netdev_warn(lif->netdev, "no intr for %s: %d\n",
513 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
515 netdev_warn(lif->netdev, "no vector for %s: %d\n",
520 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
523 err = ionic_request_irq(lif, qcq);
525 netdev_warn(lif->netdev, "irq request failed %d\n", err);
530 affinity_mask = &lif->ionic->affinity_masks[qcq->intr.index];
535 dev_to_node(lif->ionic->dev));
544 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
548 ionic_intr_free(lif->ionic, qcq->intr.index);
553 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
563 struct ionic_dev *idev = &lif->ionic->idev;
564 struct device *dev = lif->ionic->dev;
572 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
582 netdev_err(lif->netdev, "Cannot allocate queue info\n");
593 .dev = lif->ionic->dev,
597 .netdev = lif->netdev,
605 netdev_err(lif->netdev, "Cannot create page_pool\n");
613 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;
615 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
618 netdev_err(lif->netdev, "Cannot initialize queue\n");
622 err = ionic_alloc_qcq_interrupt(lif, new);
626 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
628 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
645 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
662 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
674 err = ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa,
677 netdev_err(lif->netdev,
685 netdev_err(lif->netdev, "Cannot map queue from cmb\n");
686 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order);
701 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
715 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
725 if (lif->doorbell_wa)
737 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order);
743 ionic_intr_free(lif->ionic, new->intr.index);
756 static int ionic_qcqs_alloc(struct ionic_lif *lif)
758 struct device *dev = lif->ionic->dev;
763 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
769 lif->kern_pid, NULL, &lif->adminqcq);
772 ionic_debugfs_add_qcq(lif, lif->adminqcq);
774 if (lif->ionic->nnqs_per_lif) {
776 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
782 lif->kern_pid, NULL, &lif->notifyqcq);
785 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
788 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
792 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
793 sizeof(*lif->txqcqs), GFP_KERNEL);
794 if (!lif->txqcqs)
796 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
797 sizeof(*lif->rxqcqs), GFP_KERNEL);
798 if (!lif->rxqcqs)
801 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
802 sizeof(*lif->txqstats), GFP_KERNEL);
803 if (!lif->txqstats)
805 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
806 sizeof(*lif->rxqstats), GFP_KERNEL);
807 if (!lif->rxqstats)
813 ionic_qcqs_free(lif);
830 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
832 struct device *dev = lif->ionic->dev;
839 .lif_index = cpu_to_le16(lif->index),
841 .ver = lif->qtype_info[q->type].version,
873 err = ionic_adminq_post_wait(lif, &ctx);
887 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
888 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi);
895 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
897 struct device *dev = lif->ionic->dev;
904 .lif_index = cpu_to_le16(lif->index),
906 .ver = lif->qtype_info[q->type].version,
920 q->partner = &lif->txqcqs[q->index]->q;
923 if (!lif->xdp_prog ||
924 (lif->xdp_prog->aux && lif->xdp_prog->aux->xdp_has_frags))
942 err = ionic_adminq_post_wait(lif, &ctx);
956 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
957 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi);
959 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi);
971 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
979 if (lif->hwstamp_txq)
988 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
989 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
994 txq_i = lif->ionic->ntxqs_per_lif;
997 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
1000 lif->kern_pid, NULL, &txq);
1006 ionic_link_qcq_interrupts(lif->adminqcq, txq);
1007 ionic_debugfs_add_qcq(lif, txq);
1009 lif->hwstamp_txq = txq;
1011 if (netif_running(lif->netdev)) {
1012 err = ionic_lif_txq_init(lif, txq);
1016 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
1026 ionic_lif_qcq_deinit(lif, txq);
1028 lif->hwstamp_txq = NULL;
1030 ionic_qcq_free(lif, txq);
1031 devm_kfree(lif->ionic->dev, txq);
1036 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
1044 if (lif->hwstamp_rxq)
1054 rxq_i = lif->ionic->nrxqs_per_lif;
1057 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
1060 lif->kern_pid, NULL, &rxq);
1066 ionic_link_qcq_interrupts(lif->adminqcq, rxq);
1067 ionic_debugfs_add_qcq(lif, rxq);
1069 lif->hwstamp_rxq = rxq;
1071 if (netif_running(lif->netdev)) {
1072 err = ionic_lif_rxq_init(lif, rxq);
1076 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
1087 ionic_lif_qcq_deinit(lif, rxq);
1089 lif->hwstamp_rxq = NULL;
1091 ionic_qcq_free(lif, rxq);
1092 devm_kfree(lif->ionic->dev, rxq);
1097 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
1101 ionic_init_queue_params(lif, &qparam);
1109 if (!netif_running(lif->netdev)) {
1110 lif->rxq_features = qparam.rxq_features;
1114 return ionic_reconfigure_queues(lif, &qparam);
1117 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
1123 .index = cpu_to_le16(lif->index),
1129 return ionic_adminq_post_wait(lif, &ctx);
1132 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
1138 .lif_index = cpu_to_le16(lif->index),
1145 spin_lock_bh(&lif->rx_filters.lock);
1147 f = ionic_rx_filter_rxsteer(lif);
1149 spin_unlock_bh(&lif->rx_filters.lock);
1154 ionic_rx_filter_free(lif, f);
1156 spin_unlock_bh(&lif->rx_filters.lock);
1158 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);
1162 err = ionic_adminq_post_wait(lif, &ctx);
1164 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
1167 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1173 .lif_index = cpu_to_le16(lif->index),
1182 if (!lif->hwstamp_rxq)
1185 qtype = lif->hwstamp_rxq->q.type;
1188 qid = lif->hwstamp_rxq->q.index;
1191 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
1192 err = ionic_adminq_post_wait(lif, &ctx);
1196 spin_lock_bh(&lif->rx_filters.lock);
1197 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED);
1198 spin_unlock_bh(&lif->rx_filters.lock);
1203 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1205 ionic_lif_del_hwstamp_rxfilt(lif);
1210 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
1216 struct ionic_lif *lif = napi_to_cq(napi)->lif;
1217 struct ionic_dev *idev = &lif->ionic->idev;
1227 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
1228 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
1231 spin_lock_irqsave(&lif->adminq_lock, irqflags);
1232 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
1233 a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
1236 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
1238 if (lif->hwstamp_rxq)
1239 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
1242 if (lif->hwstamp_txq)
1243 tx_work = ionic_tx_cq_service(&lif->hwstamp_txq->cq, budget, !!budget);
1257 if (lif->doorbell_wa) {
1259 ionic_adminq_poke_doorbell(&lif->adminqcq->q);
1260 if (lif->hwstamp_rxq && !rx_work)
1261 ionic_rxq_poke_doorbell(&lif->hwstamp_rxq->q);
1262 if (lif->hwstamp_txq && !tx_work)
1263 ionic_txq_poke_doorbell(&lif->hwstamp_txq->q);
1272 struct ionic_lif *lif = netdev_priv(netdev);
1276 ls = &lif->info->stats;
1336 void ionic_lif_rx_mode(struct ionic_lif *lif)
1338 struct net_device *netdev = lif->netdev;
1346 mutex_lock(&lif->config_lock);
1358 ionic_rx_filter_sync(lif);
1366 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1368 if (((lif->nucast + lif->nmcast) >= nfilters) ||
1369 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) {
1380 lif->rx_mode, rx_mode);
1393 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);
1395 if (lif->rx_mode != rx_mode) {
1400 .lif_index = cpu_to_le16(lif->index),
1406 err = ionic_adminq_post_wait(lif, &ctx);
1411 lif->rx_mode = rx_mode;
1414 mutex_unlock(&lif->config_lock);
1419 struct ionic_lif *lif = netdev_priv(netdev);
1431 netdev_err(lif->netdev, "rxmode change dropped\n");
1435 netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1436 ionic_lif_deferred_enqueue(lif, work);
1479 static int ionic_set_nic_features(struct ionic_lif *lif,
1482 struct device *dev = lif->ionic->dev;
1487 .index = cpu_to_le16(lif->index),
1499 if (lif->phc)
1502 err = ionic_adminq_post_wait(lif, &ctx);
1506 old_hw_features = lif->hw_features;
1507 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1510 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1511 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1515 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1517 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1519 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1521 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1523 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1525 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1527 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1529 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1531 if (lif->hw_features & IONIC_ETH_HW_TSO)
1533 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1535 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1537 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1539 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1541 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1543 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1545 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1547 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1549 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
1555 static int ionic_init_nic_features(struct ionic_lif *lif)
1557 struct net_device *netdev = lif->netdev;
1578 if (lif->nxqs > 1)
1581 err = ionic_set_nic_features(lif, features);
1588 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1590 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1592 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1594 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1596 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1599 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1601 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1603 if (lif->hw_features & IONIC_ETH_HW_TSO)
1605 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1607 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1609 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1611 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1613 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1615 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1617 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1619 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1641 struct ionic_lif *lif = netdev_priv(netdev);
1644 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1645 __func__, (u64)lif->netdev->features, (u64)features);
1647 err = ionic_set_nic_features(lif, features);
1652 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac)
1658 .index = cpu_to_le16(lif->index),
1664 return ionic_adminq_post_wait(lif, &ctx);
1667 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr)
1673 .index = cpu_to_le16(lif->index),
1679 err = ionic_adminq_post_wait(lif, &ctx);
1687 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac)
1692 err = ionic_set_attr_mac(lif, mac);
1696 err = ionic_get_attr_mac(lif, get_mac);
1712 struct ionic_lif *lif = netdev_priv(netdev);
1721 err = ionic_program_mac(lif, mac);
1745 void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1748 netif_device_detach(lif->netdev);
1749 ionic_stop_queues(lif);
1750 ionic_txrx_deinit(lif);
1753 static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1765 err = ionic_txrx_init(lif);
1766 ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1767 netif_device_attach(lif->netdev);
1772 static bool ionic_xdp_is_valid_mtu(struct ionic_lif *lif, u32 mtu,
1789 struct ionic_lif *lif = netdev_priv(netdev);
1794 .index = cpu_to_le16(lif->index),
1802 xdp_prog = READ_ONCE(lif->xdp_prog);
1803 if (!ionic_xdp_is_valid_mtu(lif, new_mtu, xdp_prog))
1806 err = ionic_adminq_post_wait(lif, &ctx);
1816 mutex_lock(&lif->queue_lock);
1817 ionic_stop_queues_reconfig(lif);
1819 err = ionic_start_queues_reconfig(lif);
1820 mutex_unlock(&lif->queue_lock);
1827 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1830 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1836 if (!netif_running(lif->netdev))
1839 mutex_lock(&lif->queue_lock);
1840 ionic_stop_queues_reconfig(lif);
1841 err = ionic_start_queues_reconfig(lif);
1842 mutex_unlock(&lif->queue_lock);
1845 dev_err(lif->ionic->dev, "%s: Restarting queues failed\n", __func__);
1850 struct ionic_lif *lif = netdev_priv(netdev);
1852 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
1853 schedule_work(&lif->tx_timeout_work);
1859 struct ionic_lif *lif = netdev_priv(netdev);
1862 err = ionic_lif_vlan_add(lif, vid);
1866 ionic_lif_rx_mode(lif);
1874 struct ionic_lif *lif = netdev_priv(netdev);
1877 err = ionic_lif_vlan_del(lif, vid);
1881 ionic_lif_rx_mode(lif);
1886 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1894 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1899 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1900 lif->rss_types = types;
1905 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1908 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1910 lif->rss_ind_tbl[i] = indir[i];
1913 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1916 return ionic_adminq_post_wait(lif, &ctx);
1919 static int ionic_lif_rss_init(struct ionic_lif *lif)
1924 lif->rss_types = IONIC_RSS_TYPE_IPV4 |
1932 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1934 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1936 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1939 static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1943 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1944 memset(lif->rss_ind_tbl, 0, tbl_sz);
1945 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1947 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1950 static void ionic_lif_quiesce(struct ionic_lif *lif)
1956 .index = cpu_to_le16(lif->index),
1963 err = ionic_adminq_post_wait(lif, &ctx);
1965 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err);
1968 static void ionic_txrx_disable(struct ionic_lif *lif)
1973 if (lif->txqcqs) {
1974 for (i = 0; i < lif->nxqs; i++)
1975 err = ionic_qcq_disable(lif, lif->txqcqs[i], err);
1978 if (lif->hwstamp_txq)
1979 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err);
1981 if (lif->rxqcqs) {
1982 for (i = 0; i < lif->nxqs; i++)
1983 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
1986 if (lif->hwstamp_rxq)
1987 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err);
1989 ionic_lif_quiesce(lif);
1992 static void ionic_txrx_deinit(struct ionic_lif *lif)
1996 if (lif->txqcqs) {
1997 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
1998 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1999 ionic_tx_flush(&lif->txqcqs[i]->cq);
2000 ionic_tx_empty(&lif->txqcqs[i]->q);
2004 if (lif->rxqcqs) {
2005 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
2006 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
2007 ionic_rx_empty(&lif->rxqcqs[i]->q);
2010 lif->rx_mode = 0;
2012 if (lif->hwstamp_txq) {
2013 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
2014 ionic_tx_flush(&lif->hwstamp_txq->cq);
2015 ionic_tx_empty(&lif->hwstamp_txq->q);
2018 if (lif->hwstamp_rxq) {
2019 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
2020 ionic_rx_empty(&lif->hwstamp_rxq->q);
2024 void ionic_txrx_free(struct ionic_lif *lif)
2028 if (lif->txqcqs) {
2029 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
2030 ionic_qcq_free(lif, lif->txqcqs[i]);
2031 devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
2032 lif->txqcqs[i] = NULL;
2036 if (lif->rxqcqs) {
2037 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
2038 ionic_qcq_free(lif, lif->rxqcqs[i]);
2039 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
2040 lif->rxqcqs[i] = NULL;
2044 if (lif->hwstamp_txq) {
2045 ionic_qcq_free(lif, lif->hwstamp_txq);
2046 devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
2047 lif->hwstamp_txq = NULL;
2050 if (lif->hwstamp_rxq) {
2051 ionic_qcq_free(lif, lif->hwstamp_rxq);
2052 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq);
2053 lif->hwstamp_rxq = NULL;
2057 static int ionic_txrx_alloc(struct ionic_lif *lif)
2063 num_desc = lif->ntxq_descs;
2067 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2068 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2076 if (test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state))
2079 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2082 for (i = 0; i < lif->nxqs; i++) {
2083 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2086 lif->kern_pid, NULL, &lif->txqcqs[i]);
2091 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2092 lif->txqcqs[i]->intr.index,
2093 lif->tx_coalesce_hw);
2094 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2095 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2098 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2103 if (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state))
2106 num_desc = lif->nrxq_descs;
2111 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2114 for (i = 0; i < lif->nxqs; i++) {
2115 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
2118 lif->kern_pid, lif->xdp_prog,
2119 &lif->rxqcqs[i]);
2123 lif->rxqcqs[i]->q.features = lif->rxq_features;
2125 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2126 lif->rxqcqs[i]->intr.index,
2127 lif->rx_coalesce_hw);
2128 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
2129 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
2131 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2132 ionic_link_qcq_interrupts(lif->rxqcqs[i],
2133 lif->txqcqs[i]);
2135 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2141 ionic_txrx_free(lif);
2146 static int ionic_txrx_init(struct ionic_lif *lif)
2151 for (i = 0; i < lif->nxqs; i++) {
2152 err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
2156 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
2158 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2163 if (lif->netdev->features & NETIF_F_RXHASH)
2164 ionic_lif_rss_init(lif);
2166 ionic_lif_rx_mode(lif);
2172 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2173 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
2179 static int ionic_txrx_enable(struct ionic_lif *lif)
2184 ionic_xdp_rxqs_prog_update(lif);
2186 for (i = 0; i < lif->nxqs; i++) {
2187 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
2188 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
2193 ionic_rx_fill(&lif->rxqcqs[i]->q,
2194 READ_ONCE(lif->rxqcqs[i]->q.xdp_prog));
2195 err = ionic_qcq_enable(lif->rxqcqs[i]);
2199 err = ionic_qcq_enable(lif->txqcqs[i]);
2201 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
2206 if (lif->hwstamp_rxq) {
2207 ionic_rx_fill(&lif->hwstamp_rxq->q, NULL);
2208 err = ionic_qcq_enable(lif->hwstamp_rxq);
2213 if (lif->hwstamp_txq) {
2214 err = ionic_qcq_enable(lif->hwstamp_txq);
2222 if (lif->hwstamp_rxq)
2223 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr);
2225 i = lif->nxqs;
2228 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr);
2229 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr);
2232 ionic_xdp_rxqs_prog_update(lif);
2237 static int ionic_start_queues(struct ionic_lif *lif)
2241 if (test_bit(IONIC_LIF_F_BROKEN, lif->state))
2244 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2247 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
2250 err = ionic_txrx_enable(lif);
2252 clear_bit(IONIC_LIF_F_UP, lif->state);
2255 netif_tx_wake_all_queues(lif->netdev);
2262 struct ionic_lif *lif = netdev_priv(netdev);
2266 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
2269 mutex_lock(&lif->queue_lock);
2271 err = ionic_txrx_alloc(lif);
2275 err = ionic_txrx_init(lif);
2279 err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
2283 err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
2289 err = ionic_start_queues(lif);
2297 ionic_lif_hwstamp_recreate_queues(lif);
2299 mutex_unlock(&lif->queue_lock);
2304 ionic_txrx_deinit(lif);
2306 ionic_txrx_free(lif);
2308 mutex_unlock(&lif->queue_lock);
2312 static void ionic_stop_queues(struct ionic_lif *lif)
2314 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
2317 netif_tx_disable(lif->netdev);
2318 ionic_txrx_disable(lif);
2323 struct ionic_lif *lif = netdev_priv(netdev);
2325 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2328 mutex_lock(&lif->queue_lock);
2329 ionic_stop_queues(lif);
2330 ionic_txrx_deinit(lif);
2331 ionic_txrx_free(lif);
2332 mutex_unlock(&lif->queue_lock);
2339 struct ionic_lif *lif = netdev_priv(netdev);
2343 return ionic_lif_hwstamp_set(lif, ifr);
2345 return ionic_lif_hwstamp_get(lif, ifr);
2354 struct ionic_lif *lif = netdev_priv(netdev);
2355 struct ionic *ionic = lif->ionic;
2385 struct ionic_lif *lif = netdev_priv(netdev);
2386 struct ionic *ionic = lif->ionic;
2422 struct ionic_lif *lif = netdev_priv(netdev);
2423 struct ionic *ionic = lif->ionic;
2454 struct ionic_lif *lif = netdev_priv(netdev);
2455 struct ionic *ionic = lif->ionic;
2493 struct ionic_lif *lif = netdev_priv(netdev);
2494 struct ionic *ionic = lif->ionic;
2525 struct ionic_lif *lif = netdev_priv(netdev);
2526 struct ionic *ionic = lif->ionic;
2553 struct ionic_lif *lif = netdev_priv(netdev);
2554 struct ionic *ionic = lif->ionic;
2581 struct ionic_lif *lif = netdev_priv(netdev);
2582 struct ionic *ionic = lif->ionic;
2621 static void ionic_vf_attr_replay(struct ionic_lif *lif)
2624 struct ionic *ionic = lif->ionic;
2714 err = xdp_rxq_info_reg(rxq_info, q->lif->netdev, q->index, napi_id);
2716 netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg failed, err %d\n",
2723 netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg_mem_model failed, err %d\n",
2738 static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif)
2743 if (!lif->rxqcqs)
2746 xdp_prog = READ_ONCE(lif->xdp_prog);
2747 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
2748 struct ionic_queue *q = &lif->rxqcqs[i]->q;
2756 struct ionic_lif *lif = netdev_priv(netdev);
2760 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) {
2763 netdev_info(lif->netdev, XDP_ERR_SPLIT);
2767 if (!ionic_xdp_is_valid_mtu(lif, netdev->mtu, bpf->prog)) {
2770 netdev_info(lif->netdev, XDP_ERR_MTU);
2774 maxfs = __le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN;
2780 old_prog = xchg(&lif->xdp_prog, bpf->prog);
2781 } else if (lif->xdp_prog && bpf->prog) {
2782 old_prog = xchg(&lif->xdp_prog, bpf->prog);
2783 ionic_xdp_rxqs_prog_update(lif);
2787 ionic_init_queue_params(lif, &qparams);
2789 mutex_lock(&lif->queue_lock);
2790 ionic_reconfigure_queues(lif, &qparams);
2791 old_prog = xchg(&lif->xdp_prog, bpf->prog);
2792 mutex_unlock(&lif->queue_lock);
2837 static int ionic_cmb_reconfig(struct ionic_lif *lif,
2850 ionic_init_queue_params(lif, &start_qparams);
2853 ionic_stop_queues_reconfig(lif);
2854 ionic_txrx_free(lif);
2857 ionic_set_queue_params(lif, qparam);
2859 if (netif_running(lif->netdev)) {
2861 err = ionic_txrx_alloc(lif);
2863 dev_warn(lif->ionic->dev,
2867 ionic_set_queue_params(lif, &start_qparams);
2868 err = ionic_txrx_alloc(lif);
2870 dev_err(lif->ionic->dev,
2876 err = ionic_start_queues_reconfig(lif);
2878 dev_err(lif->ionic->dev,
2886 netif_device_attach(lif->netdev);
2932 ionic_debugfs_add_qcq(a->q.lif, a);
2935 int ionic_reconfigure_queues(struct ionic_lif *lif,
2945 if ((test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && qparam->cmb_tx) ||
2946 (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state) && qparam->cmb_rx))
2947 return ionic_cmb_reconfig(lif, qparam);
2950 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2951 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
2958 if (qparam->nxqs != lif->nxqs ||
2959 qparam->nrxq_descs != lif->nrxq_descs ||
2960 qparam->rxq_features != lif->rxq_features ||
2961 qparam->xdp_prog != lif->xdp_prog) {
2962 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
2978 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2979 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2987 if (!lif->txqcqs[i]) {
2989 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2992 lif->kern_pid, NULL, &lif->txqcqs[i]);
2997 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2998 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
3001 lif->kern_pid, NULL, &tx_qcqs[i]);
3018 if (!lif->rxqcqs[i]) {
3020 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
3023 lif->kern_pid, NULL, &lif->rxqcqs[i]);
3028 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
3029 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
3032 lif->kern_pid, qparam->xdp_prog, &rx_qcqs[i]);
3042 ionic_stop_queues_reconfig(lif);
3044 if (qparam->nxqs != lif->nxqs) {
3045 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
3048 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
3050 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
3057 lif->ntxq_descs = qparam->ntxq_descs;
3059 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
3063 lif->nrxq_descs = qparam->nrxq_descs;
3065 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
3069 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
3070 qparam->nxqs != lif->nxqs) {
3072 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
3074 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
3075 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
3076 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
3083 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
3084 if (lif->txqcqs[i])
3085 ionic_qcq_intr_free(lif, lif->txqcqs[i]);
3086 if (lif->rxqcqs[i])
3087 ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
3092 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
3093 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
3094 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
3095 lif->rxqcqs[i]->intr.index,
3096 lif->rx_coalesce_hw);
3099 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
3100 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
3101 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
3102 lif->txqcqs[i]->intr.index,
3103 lif->tx_coalesce_hw);
3104 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
3105 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
3107 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3108 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
3116 ionic_debugfs_del_qcq(lif->txqcqs[i]);
3117 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
3123 ionic_debugfs_del_qcq(lif->rxqcqs[i]);
3124 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
3128 swap(lif->nxqs, qparam->nxqs);
3129 swap(lif->rxq_features, qparam->rxq_features);
3134 ionic_start_queues_reconfig(lif);
3136 err = ionic_start_queues_reconfig(lif);
3143 ionic_qcq_free(lif, tx_qcqs[i]);
3144 devm_kfree(lif->ionic->dev, tx_qcqs[i]);
3149 ionic_qcq_free(lif, rx_qcqs[i]);
3150 devm_kfree(lif->ionic->dev, rx_qcqs[i]);
3157 devm_kfree(lif->ionic->dev, rx_qcqs);
3161 devm_kfree(lif->ionic->dev, tx_qcqs);
3168 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
3169 if (lif->txqcqs && lif->txqcqs[i]) {
3170 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3171 ionic_qcq_free(lif, lif->txqcqs[i]);
3174 if (lif->rxqcqs && lif->rxqcqs[i]) {
3175 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3176 ionic_qcq_free(lif, lif->rxqcqs[i]);
3181 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err);
3229 struct ionic_lif *lif;
3237 netdev = alloc_etherdev_mqs(sizeof(*lif),
3247 lif = netdev_priv(netdev);
3248 lif->netdev = netdev;
3249 ionic->lif = lif;
3250 lif->ionic = ionic;
3257 lif->identity = lid;
3258 lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
3259 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
3262 lif->lif_type, err);
3265 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
3266 le32_to_cpu(lif->identity->eth.min_frame_size));
3267 lif->netdev->max_mtu =
3268 le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN;
3270 lif->neqs = ionic->neqs_per_lif;
3271 lif->nxqs = ionic->ntxqs_per_lif;
3273 lif->index = 0;
3276 lif->ntxq_descs = IONIC_MIN_TXRX_DESC;
3277 lif->nrxq_descs = IONIC_MIN_TXRX_DESC;
3279 lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
3280 lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
3284 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
3285 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
3286 lif->rx_coalesce_usecs);
3287 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
3288 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
3289 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
3290 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
3292 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
3294 mutex_init(&lif->queue_lock);
3295 mutex_init(&lif->config_lock);
3297 spin_lock_init(&lif->adminq_lock);
3299 spin_lock_init(&lif->deferred.lock);
3300 INIT_LIST_HEAD(&lif->deferred.list);
3301 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
3303 /* allocate lif info */
3304 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
3305 lif->info = dma_alloc_coherent(dev, lif->info_sz,
3306 &lif->info_pa, GFP_KERNEL);
3307 if (!lif->info) {
3308 dev_err(dev, "Failed to allocate lif info, aborting\n");
3313 ionic_debugfs_add_lif(lif);
3320 ionic_lif_queue_identify(lif);
3321 err = ionic_qcqs_alloc(lif);
3326 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
3327 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
3328 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
3329 &lif->rss_ind_tbl_pa,
3332 if (!lif->rss_ind_tbl) {
3337 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
3339 ionic_lif_alloc_phc(lif);
3344 ionic_qcqs_free(lif);
3346 ionic_affinity_masks_free(lif->ionic);
3348 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3349 lif->info = NULL;
3350 lif->info_pa = 0;
3352 mutex_destroy(&lif->config_lock);
3353 mutex_destroy(&lif->queue_lock);
3355 free_netdev(lif->netdev);
3356 lif = NULL;
3363 static void ionic_lif_reset(struct ionic_lif *lif)
3365 struct ionic_dev *idev = &lif->ionic->idev;
3370 mutex_lock(&lif->ionic->dev_cmd_lock);
3371 ionic_dev_cmd_lif_reset(idev, lif->index);
3372 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3373 mutex_unlock(&lif->ionic->dev_cmd_lock);
3376 static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
3378 struct ionic *ionic = lif->ionic;
3380 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
3385 netif_device_detach(lif->netdev);
3387 mutex_lock(&lif->queue_lock);
3388 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
3390 ionic_stop_queues(lif);
3393 if (netif_running(lif->netdev)) {
3394 ionic_txrx_deinit(lif);
3395 ionic_txrx_free(lif);
3397 ionic_lif_deinit(lif);
3399 ionic_qcqs_free(lif);
3401 mutex_unlock(&lif->queue_lock);
3403 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
3407 int ionic_restart_lif(struct ionic_lif *lif)
3409 struct ionic *ionic = lif->ionic;
3412 mutex_lock(&lif->queue_lock);
3414 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
3417 err = ionic_qcqs_alloc(lif);
3421 err = ionic_lif_init(lif);
3425 ionic_vf_attr_replay(lif);
3427 if (lif->registered)
3428 ionic_lif_set_netdev_info(lif);
3430 ionic_rx_filter_replay(lif);
3432 if (netif_running(lif->netdev)) {
3433 err = ionic_txrx_alloc(lif);
3437 err = ionic_txrx_init(lif);
3442 mutex_unlock(&lif->queue_lock);
3444 clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
3445 ionic_link_status_check_request(lif, CAN_SLEEP);
3446 netif_device_attach(lif->netdev);
3452 ionic_txrx_free(lif);
3454 ionic_lif_deinit(lif);
3456 ionic_qcqs_free(lif);
3458 mutex_unlock(&lif->queue_lock);
3463 static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
3465 struct ionic *ionic = lif->ionic;
3468 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3489 err = ionic_restart_lif(lif);
3496 ionic_lif_hwstamp_replay(lif);
3504 void ionic_lif_free(struct ionic_lif *lif)
3506 struct device *dev = lif->ionic->dev;
3508 ionic_lif_free_phc(lif);
3511 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
3512 lif->rss_ind_tbl_pa);
3513 lif->rss_ind_tbl = NULL;
3514 lif->rss_ind_tbl_pa = 0;
3517 ionic_qcqs_free(lif);
3518 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3519 ionic_lif_reset(lif);
3521 ionic_affinity_masks_free(lif->ionic);
3523 /* free lif info */
3524 kfree(lif->identity);
3525 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3526 lif->info = NULL;
3527 lif->info_pa = 0;
3529 mutex_destroy(&lif->config_lock);
3530 mutex_destroy(&lif->queue_lock);
3532 /* free netdev & lif */
3533 ionic_debugfs_del_lif(lif);
3534 free_netdev(lif->netdev);
3537 void ionic_lif_deinit(struct ionic_lif *lif)
3539 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
3542 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3543 cancel_work_sync(&lif->deferred.work);
3544 cancel_work_sync(&lif->tx_timeout_work);
3545 ionic_rx_filters_deinit(lif);
3546 if (lif->netdev->features & NETIF_F_RXHASH)
3547 ionic_lif_rss_deinit(lif);
3550 napi_disable(&lif->adminqcq->napi);
3551 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3552 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3554 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3555 lif->kern_dbpage = NULL;
3557 ionic_lif_reset(lif);
3560 static int ionic_lif_adminq_init(struct ionic_lif *lif)
3562 struct device *dev = lif->ionic->dev;
3569 idev = &lif->ionic->idev;
3570 qcq = lif->adminqcq;
3573 mutex_lock(&lif->ionic->dev_cmd_lock);
3574 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
3575 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3577 mutex_unlock(&lif->ionic->dev_cmd_lock);
3579 netdev_err(lif->netdev, "adminq init failed %d\n", err);
3593 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi);
3609 static int ionic_lif_notifyq_init(struct ionic_lif *lif)
3611 struct ionic_qcq *qcq = lif->notifyqcq;
3612 struct device *dev = lif->ionic->dev;
3620 .lif_index = cpu_to_le16(lif->index),
3622 .ver = lif->qtype_info[q->type].version,
3626 .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
3638 err = ionic_adminq_post_wait(lif, &ctx);
3642 lif->last_eid = 0;
3651 q->admin_info[0].ctx = lif;
3658 static int ionic_station_set(struct ionic_lif *lif)
3660 struct net_device *netdev = lif->netdev;
3665 .index = cpu_to_le16(lif->index),
3673 err = ionic_adminq_post_wait(lif, &ctx);
3676 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
3685 err = ionic_program_mac(lif, mac_address);
3703 ionic_lif_addr_add(lif, netdev->dev_addr);
3710 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
3718 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3720 ionic_lif_addr_add(lif, netdev->dev_addr);
3725 int ionic_lif_init(struct ionic_lif *lif)
3727 struct ionic_dev *idev = &lif->ionic->idev;
3728 struct device *dev = lif->ionic->dev;
3733 mutex_lock(&lif->ionic->dev_cmd_lock);
3734 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
3735 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3737 mutex_unlock(&lif->ionic->dev_cmd_lock);
3741 lif->hw_index = le16_to_cpu(comp.hw_index);
3744 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
3745 if (!lif->dbid_count) {
3750 lif->kern_pid = 0;
3751 dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
3752 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
3753 if (!lif->kern_dbpage) {
3758 err = ionic_lif_adminq_init(lif);
3762 if (lif->ionic->nnqs_per_lif) {
3763 err = ionic_lif_notifyq_init(lif);
3768 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3769 err = ionic_set_nic_features(lif, lif->netdev->features);
3771 err = ionic_init_nic_features(lif);
3775 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3776 err = ionic_rx_filters_init(lif);
3781 err = ionic_station_set(lif);
3785 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
3786 lif->doorbell_wa = ionic_doorbell_wa(lif->ionic);
3788 set_bit(IONIC_LIF_F_INITED, lif->state);
3790 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
3795 napi_disable(&lif->adminqcq->napi);
3796 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3798 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3799 ionic_lif_reset(lif);
3800 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3801 lif->kern_dbpage = NULL;
3806 static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
3812 .index = cpu_to_le16(lif->index),
3817 strscpy(ctx.cmd.lif_setattr.name, netdev_name(lif->netdev),
3820 ionic_adminq_post_wait(lif, &ctx);
3836 struct ionic_lif *lif = ionic_netdev_lif(ndev);
3838 if (!lif || lif->ionic != ionic)
3843 ionic_lif_set_netdev_info(lif);
3850 int ionic_lif_register(struct ionic_lif *lif)
3854 ionic_lif_register_phc(lif);
3856 lif->ionic->nb.notifier_call = ionic_lif_notify;
3858 err = register_netdevice_notifier(&lif->ionic->nb);
3860 lif->ionic->nb.notifier_call = NULL;
3863 err = register_netdev(lif->netdev);
3865 dev_err(lif->ionic->dev, "Cannot register net device: %d, aborting\n", err);
3866 ionic_lif_unregister(lif);
3870 ionic_link_status_check_request(lif, CAN_SLEEP);
3871 lif->registered = true;
3872 ionic_lif_set_netdev_info(lif);
3877 void ionic_lif_unregister(struct ionic_lif *lif)
3879 if (lif->ionic->nb.notifier_call) {
3880 unregister_netdevice_notifier(&lif->ionic->nb);
3881 lif->ionic->nb.notifier_call = NULL;
3884 if (lif->netdev->reg_state == NETREG_REGISTERED)
3885 unregister_netdev(lif->netdev);
3887 ionic_lif_unregister_phc(lif);
3889 lif->registered = false;
3892 static void ionic_lif_queue_identify(struct ionic_lif *lif)
3895 struct ionic *ionic = lif->ionic;
3901 idev = &lif->ionic->idev;
3905 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3921 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
4034 lc = &ident->lif.eth.config;
4036 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
4066 * 1 for master lif adminq/notifyq
4067 * 1 for each CPU for master lif TxRx queue pairs