1249 	u32 phy_reserved;  in init_realtek_8201()  local
1252 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201()
1254 		phy_reserved |= PHY_REALTEK_INIT7;  in init_realtek_8201()
1256 			   PHY_REALTEK_INIT_REG6, phy_reserved))  in init_realtek_8201()
1265 	u32 phy_reserved;  in init_realtek_8201_cross()  local
1271 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201_cross()
1273 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in init_realtek_8201_cross()
1274 		phy_reserved |= PHY_REALTEK_INIT3;  in init_realtek_8201_cross()
1276 			   PHY_REALTEK_INIT_REG2, phy_reserved))  in init_realtek_8201_cross()
1289 	u32 phy_reserved;  in init_cicada()  local
1292 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1293 		phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);  in init_cicada()
1294 		phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);  in init_cicada()
1295 		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))  in init_cicada()
1297 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1298 		phy_reserved |= PHY_CICADA_INIT5;  in init_cicada()
1299 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))  in init_cicada()
1302 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1303 	phy_reserved |= PHY_CICADA_INIT6;  in init_cicada()
1304 	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))  in init_cicada()
1312 	u32 phy_reserved;  in init_vitesse()  local
1320 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1322 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1324 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1326 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1327 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1328 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1336 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1338 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1339 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1340 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1342 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1344 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1352 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1354 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1356 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1358 	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;  in init_vitesse()
1359 	phy_reserved |= PHY_VITESSE_INIT8;  in init_vitesse()
1360 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
6151 	u16 phy_reserved, mii_control;  in nv_restore_phy()  local
6157 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6158 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in nv_restore_phy()
6159 		phy_reserved |= PHY_REALTEK_INIT8;  in nv_restore_phy()
6160 		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);  in nv_restore_phy()