Lines Matching full:ocelot
3 * Microsemi Ocelot Switch driver
7 #include <linux/dsa/ocelot.h>
14 #include "ocelot.h"
30 /* Caller must hold &ocelot->mact_lock */
31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
36 /* Caller must hold &ocelot->mact_lock */
37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
42 ocelot, val,
48 /* Caller must hold &ocelot->mact_lock */
49 static void ocelot_mact_select(struct ocelot *ocelot,
66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
90 if (mc_ports & BIT(ocelot->num_phys_ports))
93 ocelot_mact_select(ocelot, mac, vid);
96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
98 err = ocelot_mact_wait_for_completion(ocelot);
103 int ocelot_mact_learn(struct ocelot *ocelot, int port,
109 mutex_lock(&ocelot->mact_lock);
110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
111 mutex_unlock(&ocelot->mact_lock);
117 int ocelot_mact_forget(struct ocelot *ocelot,
122 mutex_lock(&ocelot->mact_lock);
124 ocelot_mact_select(ocelot, mac, vid);
127 ocelot_write(ocelot,
131 err = ocelot_mact_wait_for_completion(ocelot);
133 mutex_unlock(&ocelot->mact_lock);
139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
145 mutex_lock(&ocelot->mact_lock);
147 ocelot_mact_select(ocelot, mac, vid);
150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
154 if (ocelot_mact_wait_for_completion(ocelot)) {
155 mutex_unlock(&ocelot->mact_lock);
160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
162 mutex_unlock(&ocelot->mact_lock);
174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
182 mutex_lock(&ocelot->mact_lock);
184 ocelot_write(ocelot,
191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
193 mutex_unlock(&ocelot->mact_lock);
199 static void ocelot_mact_init(struct ocelot *ocelot)
205 ocelot_rmw(ocelot, 0,
212 * holding &ocelot->mact_lock is pointless.
214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
217 void ocelot_pll5_init(struct ocelot *ocelot)
220 * The values are coming from the VTSS API for Ocelot
222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
267 for (port = 0; port < ocelot->num_phys_ports; port++) {
268 struct ocelot_port *ocelot_port = ocelot->ports[port];
290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
300 ocelot,
307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
317 return ocelot_vlant_wait_for_completion(ocelot);
320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
325 list_for_each_entry(vlan, &ocelot->vlans, list) {
343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
348 list_for_each_entry(vlan, &ocelot->vlans, list) {
362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
364 return ocelot_port_num_tagged_vlans(ocelot, port) &&
365 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
373 list_for_each_entry(vlan, &ocelot->vlans, list)
384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
395 else if (ocelot_port_num_untagged_vlans(ocelot, port))
403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
414 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
416 ocelot_rmw_gix(ocelot,
423 int ocelot_bridge_num_find(struct ocelot *ocelot,
428 for (port = 0; port < ocelot->num_phys_ports; port++) {
429 struct ocelot_port *ocelot_port = ocelot->ports[port];
439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
448 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
459 * @ocelot: Switch private data structure
516 static int ocelot_update_vlan_reclassify_rule(struct ocelot *ocelot, int port)
518 unsigned long cookie = OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port);
519 struct ocelot_vcap_block *block_vcap_is1 = &ocelot->block[VCAP_IS1];
520 struct ocelot_port *ocelot_port = ocelot->ports[port];
538 return ocelot_vcap_filter_del(ocelot, filter);
551 val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
575 return ocelot_vcap_filter_replace(ocelot, filter);
598 err = ocelot_vcap_filter_add(ocelot, filter, NULL);
606 static int ocelot_port_set_pvid(struct ocelot *ocelot, int port,
609 struct ocelot_port *ocelot_port = ocelot->ports[port];
610 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
618 ocelot_rmw_gix(ocelot,
637 ocelot_rmw_gix(ocelot, val,
643 return ocelot_update_vlan_reclassify_rule(ocelot, port);
646 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
651 list_for_each_entry(vlan, &ocelot->vlans, list)
658 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
661 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
668 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
691 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
702 list_add_tail(&vlan->list, &ocelot->vlans);
707 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
709 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
718 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
732 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
735 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
737 return ocelot_vlan_member_add(ocelot, port, vid, true);
740 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
743 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
745 return ocelot_vlan_member_del(ocelot, port, vid);
748 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
751 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
752 struct ocelot_port *ocelot_port = ocelot->ports[port];
766 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
771 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
774 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
786 ocelot_rmw_gix(ocelot, val,
791 err = ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
795 ocelot_port_manage_port_tag(ocelot, port);
801 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
806 if (ocelot_port_uses_native_vlan(ocelot, port)) {
813 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
830 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
833 struct ocelot_port *ocelot_port = ocelot->ports[port];
843 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
849 err = ocelot_port_set_pvid(ocelot, port,
850 ocelot_bridge_vlan_find(ocelot, vid));
854 ocelot_bridge_vlan_find(ocelot, vid) == ocelot_port->pvid_vlan) {
855 err = ocelot_port_set_pvid(ocelot, port, NULL);
861 ocelot_port_manage_port_tag(ocelot, port);
867 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
869 struct ocelot_port *ocelot_port = ocelot->ports[port];
879 err = ocelot_vlan_member_del(ocelot, port, vid);
885 err = ocelot_port_set_pvid(ocelot, port, NULL);
891 ocelot_port_manage_port_tag(ocelot, port);
897 static void ocelot_vlan_init(struct ocelot *ocelot)
899 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
903 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
905 ocelot_vlant_wait_for_completion(ocelot);
909 ocelot_vlant_set_mask(ocelot, vid, 0);
915 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
920 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
922 for (port = 0; port < ocelot->num_phys_ports; port++) {
923 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
924 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
928 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
930 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
933 static int ocelot_port_flush(struct ocelot *ocelot, int port)
939 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
944 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
945 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
948 ocelot_fields_write(ocelot, port,
962 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
966 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
970 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
975 100, 2000000, false, ocelot, port);
978 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
981 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
986 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
989 struct ocelot_port *ocelot_port = ocelot->ports[port];
990 struct device *dev = ocelot->dev;
1025 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
1029 struct ocelot_port *ocelot_port = ocelot->ports[port];
1051 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1056 struct ocelot_port *ocelot_port = ocelot->ports[port];
1064 if (ocelot->ops->cut_through_fwd) {
1065 mutex_lock(&ocelot->fwd_domain_lock);
1066 ocelot->ops->cut_through_fwd(ocelot);
1067 mutex_unlock(&ocelot->fwd_domain_lock);
1070 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
1072 err = ocelot_port_flush(ocelot, port);
1074 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
1089 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1097 struct ocelot_port *ocelot_port = ocelot->ports[port];
1144 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
1161 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
1163 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
1166 if (port != ocelot->npi)
1167 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
1179 if (ocelot->ops->cut_through_fwd) {
1180 mutex_lock(&ocelot->fwd_domain_lock);
1183 * below also calls ocelot->ops->cut_through_fwd(),
1186 ocelot_port_update_active_preemptible_tcs(ocelot, port);
1187 mutex_unlock(&ocelot->fwd_domain_lock);
1191 ocelot_fields_write(ocelot, port,
1196 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1201 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1207 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1220 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1222 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1228 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1238 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1243 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1251 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1258 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1274 void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp)
1275 __acquires(&ocelot->inj_lock)
1277 spin_lock(&ocelot->inj_lock);
1281 void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp)
1282 __releases(&ocelot->inj_lock)
1284 spin_unlock(&ocelot->inj_lock);
1288 void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp)
1289 __acquires(&ocelot->inj_lock)
1291 spin_lock(&ocelot->inj_lock);
1295 void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp)
1296 __releases(&ocelot->inj_lock)
1298 spin_unlock(&ocelot->inj_lock);
1302 void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1303 __acquires(&ocelot->xtr_lock)
1305 spin_lock_bh(&ocelot->xtr_lock);
1309 void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1310 __releases(&ocelot->xtr_lock)
1312 spin_unlock_bh(&ocelot->xtr_lock);
1316 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1326 lockdep_assert_held(&ocelot->xtr_lock);
1328 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1336 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1339 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1354 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1364 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1378 if (ocelot->ptp)
1379 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1384 if (ocelot->ports[src_port]->bridge)
1399 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1401 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1403 lockdep_assert_held(&ocelot->inj_lock);
1417 * @ocelot: Switch private data structure
1425 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port,
1428 struct ocelot_port *ocelot_port = ocelot->ports[port];
1441 ocelot_ifh_set_src(ifh, ocelot->num_phys_ports);
1451 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1457 lockdep_assert_held(&ocelot->inj_lock);
1459 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1462 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb);
1465 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1470 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1474 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1479 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1485 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1493 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1495 lockdep_assert_held(&ocelot->xtr_lock);
1497 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1498 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1502 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1506 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1508 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1512 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1516 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1518 return ocelot_mact_forget(ocelot, addr, vid);
1522 /* Caller must hold &ocelot->mact_lock */
1523 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1530 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1531 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1534 ocelot_write(ocelot,
1538 if (ocelot_mact_wait_for_completion(ocelot))
1542 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1554 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1555 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1570 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1574 mutex_lock(&ocelot->mact_lock);
1577 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1581 ocelot_write(ocelot,
1585 err = ocelot_mact_wait_for_completion(ocelot);
1587 mutex_unlock(&ocelot->mact_lock);
1592 ocelot_write(ocelot,
1596 err = ocelot_mact_wait_for_completion(ocelot);
1599 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1601 mutex_unlock(&ocelot->mact_lock);
1607 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1616 mutex_lock(&ocelot->mact_lock);
1619 for (i = 0; i < ocelot->num_mact_rows; i++) {
1624 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1647 mutex_unlock(&ocelot->mact_lock);
1653 int ocelot_trap_add(struct ocelot *ocelot, int port,
1662 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1689 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1691 err = ocelot_vcap_filter_replace(ocelot, trap);
1702 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1707 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1716 return ocelot_vcap_filter_del(ocelot, trap);
1718 return ocelot_vcap_filter_replace(ocelot, trap);
1721 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1726 lockdep_assert_held(&ocelot->fwd_domain_lock);
1728 for (port = 0; port < ocelot->num_phys_ports; port++) {
1729 struct ocelot_port *ocelot_port = ocelot->ports[port];
1744 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1746 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1765 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1771 for (port = 0; port < ocelot->num_phys_ports; port++) {
1772 struct ocelot_port *ocelot_port = ocelot->ports[port];
1782 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1790 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1792 struct ocelot_port *ocelot_port = ocelot->ports[port];
1799 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1805 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1807 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1819 for (port = 0; port < ocelot->num_phys_ports; port++) {
1820 ocelot_port = ocelot->ports[port];
1834 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1838 lockdep_assert_held(&ocelot->fwd_domain_lock);
1844 if (joining && ocelot->ops->cut_through_fwd)
1845 ocelot->ops->cut_through_fwd(ocelot);
1850 for (port = 0; port < ocelot->num_phys_ports; port++) {
1851 struct ocelot_port *ocelot_port = ocelot->ports[port];
1861 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1866 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1869 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1873 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1879 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1883 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1893 if (!joining && ocelot->ops->cut_through_fwd)
1894 ocelot->ops->cut_through_fwd(ocelot);
1904 static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1909 for (port = 0; port < ocelot->num_phys_ports; port++) {
1910 struct ocelot_port *ocelot_port = ocelot->ports[port];
1919 pgid_cpu = BIT(ocelot->num_phys_ports);
1921 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1924 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1926 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1929 mutex_lock(&ocelot->fwd_domain_lock);
1934 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1936 ocelot_update_pgid_cpu(ocelot);
1938 mutex_unlock(&ocelot->fwd_domain_lock);
1942 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1944 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1947 mutex_lock(&ocelot->fwd_domain_lock);
1952 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1954 ocelot_update_pgid_cpu(ocelot);
1956 mutex_unlock(&ocelot->fwd_domain_lock);
1960 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1963 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1965 mutex_lock(&ocelot->fwd_domain_lock);
1967 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1968 ocelot_apply_bridge_fwd_mask(ocelot, true);
1970 mutex_unlock(&ocelot->fwd_domain_lock);
1974 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1976 mutex_lock(&ocelot->fwd_domain_lock);
1978 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1979 ocelot_apply_bridge_fwd_mask(ocelot, true);
1981 mutex_unlock(&ocelot->fwd_domain_lock);
1985 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1987 struct ocelot_port *ocelot_port = ocelot->ports[port];
1990 mutex_lock(&ocelot->fwd_domain_lock);
1998 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
2001 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
2003 mutex_unlock(&ocelot->fwd_domain_lock);
2007 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
2017 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
2021 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
2027 list_for_each_entry(mc, &ocelot->multicast, list) {
2044 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
2056 list_add_tail(&pgid->list, &ocelot->pgids);
2061 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
2070 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
2083 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
2085 list_for_each_entry(pgid, &ocelot->pgids, list) {
2096 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
2099 list_for_each_entry(pgid, &ocelot->pgids, list) {
2107 return ocelot_pgid_alloc(ocelot, index, mc->ports);
2128 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
2138 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2140 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2143 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
2151 list_add_tail(&mc->list, &ocelot->multicast);
2156 ocelot_pgid_free(ocelot, mc->pgid);
2158 ocelot_mact_forget(ocelot, addr, vid);
2163 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2165 dev_err(ocelot->dev,
2168 devm_kfree(ocelot->dev, mc);
2177 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2180 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2185 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2195 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2197 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2202 ocelot_mact_forget(ocelot, addr, vid);
2204 ocelot_pgid_free(ocelot, mc->pgid);
2208 devm_kfree(ocelot->dev, mc);
2213 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2222 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2225 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2230 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2234 struct ocelot_port *ocelot_port = ocelot->ports[port];
2237 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
2241 mutex_lock(&ocelot->fwd_domain_lock);
2246 ocelot_apply_bridge_fwd_mask(ocelot, true);
2248 mutex_unlock(&ocelot->fwd_domain_lock);
2253 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2257 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2260 struct ocelot_port *ocelot_port = ocelot->ports[port];
2262 mutex_lock(&ocelot->fwd_domain_lock);
2265 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2270 ocelot_port_set_pvid(ocelot, port, NULL);
2271 ocelot_port_manage_port_tag(ocelot, port);
2272 ocelot_apply_bridge_fwd_mask(ocelot, false);
2274 mutex_unlock(&ocelot->fwd_domain_lock);
2278 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2280 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2284 for_each_unicast_dest_pgid(ocelot, port)
2285 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2287 for_each_aggr_pgid(ocelot, i)
2288 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2299 for (port = 0; port < ocelot->num_phys_ports; port++) {
2300 struct ocelot_port *ocelot_port = ocelot->ports[port];
2309 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2310 struct net_device *bond = ocelot->ports[lag]->bond;
2318 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2320 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2321 struct ocelot_port *ocelot_port = ocelot->ports[port];
2324 ocelot_write_rix(ocelot, bond_mask,
2331 for_each_aggr_pgid(ocelot, i) {
2334 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2341 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2347 for (port = lag; port < ocelot->num_phys_ports; port++) {
2348 struct ocelot_port *ocelot_port = ocelot->ports[port];
2364 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2368 for (port = 0; port < ocelot->num_phys_ports; port++) {
2369 struct ocelot_port *ocelot_port = ocelot->ports[port];
2377 int lag = ocelot_bond_get_id(ocelot, bond);
2379 ocelot_rmw_gix(ocelot,
2384 ocelot_rmw_gix(ocelot,
2392 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2399 dev_dbg(ocelot->dev,
2406 ocelot_pgid_free(ocelot, mc->pgid);
2408 ocelot_mact_forget(ocelot, addr, vid);
2413 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2415 dev_err(ocelot->dev,
2418 devm_kfree(ocelot->dev, mc);
2427 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2430 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2434 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2440 list_for_each_entry(mc, &ocelot->multicast, list) {
2444 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2463 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2470 lockdep_assert_held(&ocelot->fwd_domain_lock);
2472 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2476 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2478 dev_err(ocelot->dev,
2483 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2486 dev_err(ocelot->dev,
2493 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2504 mutex_lock(&ocelot->fwd_domain_lock);
2506 ocelot->ports[port]->bond = bond;
2508 ocelot_setup_logical_port_ids(ocelot);
2509 ocelot_apply_bridge_fwd_mask(ocelot, true);
2510 ocelot_set_aggr_pgids(ocelot);
2512 mutex_unlock(&ocelot->fwd_domain_lock);
2518 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2523 mutex_lock(&ocelot->fwd_domain_lock);
2525 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2527 ocelot->ports[port]->bond = NULL;
2529 ocelot_setup_logical_port_ids(ocelot);
2530 ocelot_apply_bridge_fwd_mask(ocelot, false);
2531 ocelot_set_aggr_pgids(ocelot);
2533 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2536 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2538 mutex_unlock(&ocelot->fwd_domain_lock);
2542 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2544 struct ocelot_port *ocelot_port = ocelot->ports[port];
2546 mutex_lock(&ocelot->fwd_domain_lock);
2551 ocelot_set_aggr_pgids(ocelot);
2553 mutex_unlock(&ocelot->fwd_domain_lock);
2557 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2568 mutex_lock(&ocelot->fwd_domain_lock);
2571 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2577 lag = ocelot_bond_get_id(ocelot, bond);
2579 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2581 mutex_unlock(&ocelot->fwd_domain_lock);
2586 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2587 mutex_unlock(&ocelot->fwd_domain_lock);
2593 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2599 mutex_lock(&ocelot->fwd_domain_lock);
2602 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2604 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2609 ocelot_mact_forget(ocelot, addr, vid);
2611 mutex_unlock(&ocelot->fwd_domain_lock);
2617 mutex_unlock(&ocelot->fwd_domain_lock);
2629 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2631 struct ocelot_port *ocelot_port = ocelot->ports[port];
2636 if (port == ocelot->npi) {
2639 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2641 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2650 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2652 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2656 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2659 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2660 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2664 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2668 if (port == ocelot->npi) {
2671 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2673 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2681 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2684 struct ocelot_port *ocelot_port = ocelot->ports[port];
2690 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2696 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2704 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2707 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2715 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2716 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2717 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2720 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2728 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2731 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2742 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2746 ocelot_port_set_learning(ocelot, port,
2750 ocelot_port_set_ucast_flood(ocelot, port,
2754 ocelot_port_set_mcast_flood(ocelot, port,
2758 ocelot_port_set_bcast_flood(ocelot, port,
2763 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2765 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2771 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2776 ocelot_rmw_gix(ocelot,
2782 return ocelot_update_vlan_reclassify_rule(ocelot, port);
2786 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2788 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2789 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2798 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2811 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2826 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2832 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2838 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2840 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2855 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2858 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2873 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2879 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2882 struct ocelot_mirror *m = ocelot->mirror;
2901 ocelot->mirror = m;
2904 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2909 void ocelot_mirror_put(struct ocelot *ocelot)
2911 struct ocelot_mirror *m = ocelot->mirror;
2916 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2917 ocelot->mirror = NULL;
2921 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2924 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2930 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2934 ocelot_rmw(ocelot, BIT(from), BIT(from),
2942 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2945 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2948 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2951 ocelot_mirror_put(ocelot);
2955 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port)
2957 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2960 ocelot_port_change_fp(ocelot, port, 0);
2963 int ocelot_port_mqprio(struct ocelot *ocelot, int port,
2966 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2973 ocelot_port_reset_mqprio(ocelot, port);
2997 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs);
3002 ocelot_port_reset_mqprio(ocelot, port);
3007 void ocelot_init_port(struct ocelot *ocelot, int port)
3009 struct ocelot_port *ocelot_port = ocelot->ports[port];
3031 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
3043 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
3046 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3051 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
3056 ocelot_port_set_learning(ocelot, port, false);
3062 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
3068 ocelot_vcap_enable(ocelot, port);
3076 static void ocelot_cpu_port_init(struct ocelot *ocelot)
3078 int cpu = ocelot->num_phys_ports;
3081 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
3086 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
3087 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
3092 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
3094 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
3096 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
3100 ocelot_write_gix(ocelot,
3107 static void ocelot_detect_features(struct ocelot *ocelot)
3111 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
3115 mmgt = ocelot_read(ocelot, SYS_MMGT);
3116 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
3118 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
3119 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
3122 static int ocelot_mem_init_status(struct ocelot *ocelot)
3127 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
3133 int ocelot_reset(struct ocelot *ocelot)
3138 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
3142 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3149 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
3154 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3158 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
3162 int ocelot_init(struct ocelot *ocelot)
3167 if (ocelot->ops->reset) {
3168 ret = ocelot->ops->reset(ocelot);
3170 dev_err(ocelot->dev, "Switch reset failed\n");
3175 mutex_init(&ocelot->mact_lock);
3176 mutex_init(&ocelot->fwd_domain_lock);
3177 spin_lock_init(&ocelot->ptp_clock_lock);
3178 spin_lock_init(&ocelot->ts_id_lock);
3179 spin_lock_init(&ocelot->inj_lock);
3180 spin_lock_init(&ocelot->xtr_lock);
3182 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
3183 if (!ocelot->owq)
3186 ret = ocelot_stats_init(ocelot);
3190 INIT_LIST_HEAD(&ocelot->multicast);
3191 INIT_LIST_HEAD(&ocelot->pgids);
3192 INIT_LIST_HEAD(&ocelot->vlans);
3193 INIT_LIST_HEAD(&ocelot->lag_fdbs);
3194 ocelot_detect_features(ocelot);
3195 ocelot_mact_init(ocelot);
3196 ocelot_vlan_init(ocelot);
3197 ocelot_vcap_init(ocelot);
3198 ocelot_cpu_port_init(ocelot);
3200 if (ocelot->ops->psfp_init)
3201 ocelot->ops->psfp_init(ocelot);
3203 if (ocelot->mm_supported) {
3204 ret = ocelot_mm_init(ocelot);
3209 for (port = 0; port < ocelot->num_phys_ports; port++) {
3211 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
3217 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
3220 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
3231 ocelot_write(ocelot,
3236 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
3239 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
3243 for (i = 0; i < ocelot->num_flooding_pgids; i++)
3244 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
3248 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3254 for (port = 0; port < ocelot->num_phys_ports; port++) {
3256 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3258 ocelot_write_gix(ocelot,
3263 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3266 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3267 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3269 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3272 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3275 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3276 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3278 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3279 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3281 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3282 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3287 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3289 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3291 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3301 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3308 ocelot_stats_deinit(ocelot);
3310 destroy_workqueue(ocelot->owq);
3315 void ocelot_deinit(struct ocelot *ocelot)
3317 ocelot_stats_deinit(ocelot);
3318 destroy_workqueue(ocelot->owq);
3322 void ocelot_deinit_port(struct ocelot *ocelot, int port)
3324 struct ocelot_port *ocelot_port = ocelot->ports[port];
3330 MODULE_DESCRIPTION("Microsemi Ocelot switch family library");